[coreboot-gerrit] Patch set updated for coreboot: nb/x4x: Fix raminit reset

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17624

-gerrit

commit 077cb9859bfd6ec79d8bee8da4c85c57d382f0e8
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Sun Nov 27 22:29:01 2016 +0100

    nb/x4x: Fix raminit reset
    
    All the other Intel raminits reset when bit7 of pmcon2 is set to 1.
    
    NOT TESTED.
    
    Change-Id: Ic014533aef7e75742ff7685020d9777dbdd1369f
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/northbridge/intel/x4x/raminit_ddr2.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index b3ee34a..9638ad7 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -260,8 +260,9 @@ static void checkreset_ddr2(struct sysinfo *s)
 	u8 reset = 0;
 
 	pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
-	if (!(pmcon2 & 0x80)) {
-		pmcon2 |= 0x80;
+	/* Do we want to reset at S4-assertion-width violation (1 << 2)? */
+	if (pmcon2 & 0x80) {
+		pmcon2 &= ~0x80;
 		pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
 		reset = 1;