[coreboot-gerrit] Patch set updated for coreboot: nb/intel/gm45: Fix panel-power-sequence clock divisor

[Nico Huber (nico.h@gmx.de)]

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17619

-gerrit

commit 9bae887904ffd7cfce885e53b02cdb1ef014c9a7
Author: Nico Huber <nico.h at gmx.de>
Date:   Sun Nov 27 14:43:12 2016 +0100

    nb/intel/gm45: Fix panel-power-sequence clock divisor
    
    We kept this value at it's default on the native graphics init path.
    Maybe the Video BIOS path, too, I don't know if the VBIOS sets it.
    
    The panel power sequencer uses the core display clock (CDCLK). It's
    based on the HPLLVCO and a frequency selection we made during raminit.
    The value written is the (actual divisor/2)-1 for a 100us timer.
    
    v2: Fix unaligned mmio access inherited from Linux.
    
    v3: Use MCHBAR8() instead. Also, the unaligned access might have
        worked after all.
    
    Change-Id: I877d229865981fb0f96c864bc79e404f6743fd05
    Signed-off-by: Nico Huber <nico.h at gmx.de>
---
 src/northbridge/intel/gm45/gm45.h    |  2 ++
 src/northbridge/intel/gm45/gma.c     | 22 ++++++++++++++++++++--
 src/northbridge/intel/gm45/raminit.c |  2 +-
 3 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index ae1863b..b9d2cb7 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -260,6 +260,8 @@ enum {
 #define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
 #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
 
+#define HPLLVCO_MCHBAR		0x0c0f
+
 #define PMSTS_MCHBAR		0x0f14	/* Self refresh channel status */
 #define PMSTS_WARM_RESET	(1 << 1)
 #define PMSTS_BOTH_SELFREFRESH	(1 << 0)
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 8938197..3e9f508 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -611,6 +611,24 @@ static u8 vga_connected(u8 *mmio)
 	return 1;
 }
 
+static u32 get_cdclk(struct device *const dev)
+{
+	const u16 cdclk_sel =
+		pci_read_config16 (dev, GCFGC_OFFSET) & GCFGC_CD_MASK;
+	switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) {
+	case VCO_2666:
+	case VCO_4000:
+	case VCO_5333:
+		return cdclk_sel ? 333333333 : 222222222;
+	case VCO_3200:
+		return cdclk_sel ? 320000000 : 228571429;
+	default:
+		printk(BIOS_WARNING,
+		       "Unknown VCO frequency, using default cdclk.\n");
+		return 222222222;
+	}
+}
+
 static void gma_pm_init_post_vbios(struct device *const dev)
 {
 	const struct northbridge_intel_gm45_config *const conf = dev->chip_info;
@@ -635,8 +653,8 @@ static void gma_pm_init_post_vbios(struct device *const dev)
 
 	/* Setup Panel Power Cycle Delay */
 	if (conf->gpu_panel_power_cycle_delay) {
-		reg32 = gtt_read(PP_DIVISOR);
-		reg32 &= ~0x1f;
+		reg32 = (get_cdclk(dev) / 20000 - 1)
+			<< PP_REFERENCE_DIVIDER_SHIFT;
 		reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f;
 		gtt_write(PP_DIVISOR, reg32);
 	}
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index daddbab..0435cdd 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -749,7 +749,7 @@ static void set_system_memory_frequency(const timings_t *const timings)
 
 int raminit_read_vco_index(void)
 {
-	switch (MCHBAR8(0x0c0f) & 0x7) {
+	switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) {
 	case VCO_2666:
 		return 0;
 	case VCO_3200: