[coreboot-gerrit] Patch set updated for coreboot: nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17597

-gerrit

commit 890998d1f51d21805ca55623fc6e38639f2ef308
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Thu Nov 24 13:23:05 2016 +0100

    nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency
    
    This allow to put a frequency value in Hz in devicetree instead of a
    plain BLC_PWM_CTL value.
    
    The previous default was 1006Hz and is now 1000Hz for simplicity.
    1000Hz is a good default since it typically works well on LED backlit
    displays. A LED backlit display with a too slow PWM causes highly
    annoying flicker. CCFL display want a lower pwm frequency in the
    50-200Hz range. Driving a CCFL panel with a too high PWM frequency
    only causes the IC to misbehave: unevenly lit backlight and/or high
    frequency tone, which is not as bad as the previous situation.
    
    Change-Id: I4d9a555ac7ea5605712c1fcda994a6fcabf9acf3
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/northbridge/intel/gm45/chip.h |  1 +
 src/northbridge/intel/gm45/gma.c  | 29 ++++++++++++++++++++++++++---
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h
index 836d6bb..d2e70f7 100644
--- a/src/northbridge/intel/gm45/chip.h
+++ b/src/northbridge/intel/gm45/chip.h
@@ -26,6 +26,7 @@ struct northbridge_intel_gm45_config {
 	u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
 	u8 gpu_panel_power_cycle_delay;          /* T4 time sequence */
 	struct i915_gpu_controller_info gfx;
+	u32 pwm_freq;
 
 	/*
 	 * Maximum PCI mmio size in MiB.
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 8938197..22cbe97 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -611,6 +611,27 @@ static u8 vga_connected(u8 *mmio)
 	return 1;
 }
 
+#define MHZ 1000000
+
+static u32 freq_to_blc_pwm_ctl(u16 pwm_freq, u16 duty_perc)
+{
+	u32 ref_divider;
+	u32 core_clock;
+	u32 blc_mod;
+
+	ref_divider = gtt_read(PP_DIVISOR) >> 8;
+	core_clock = (ref_divider + 1) / 100 * MHZ * 2;
+
+	blc_mod = core_clock / (128 * pwm_freq);
+
+	if (duty_perc <= 100)
+		return (blc_mod << 16) | (blc_mod * duty_perc / 100);
+	else
+		return (blc_mod << 16) | blc_mod;
+}
+
+#define DEFAULT_PWM_FREQ 1000
+
 static void gma_pm_init_post_vbios(struct device *const dev)
 {
 	const struct northbridge_intel_gm45_config *const conf = dev->chip_info;
@@ -643,10 +664,12 @@ static void gma_pm_init_post_vbios(struct device *const dev)
 
 	/* Enable Backlight  */
 	gtt_write(BLC_PWM_CTL2, (1 << 31));
-	if (conf->gfx.backlight == 0)
-		gtt_write(BLC_PWM_CTL, 0x06100610);
+	if (conf->pwm_freq == 0)
+		gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(DEFAULT_PWM_FREQ,
+								100));
 	else
-		gtt_write(BLC_PWM_CTL, conf->gfx.backlight);
+		gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(conf->pwm_freq,
+								100));
 }
 
 static void gma_func0_init(struct device *dev)