[coreboot-gerrit] New patch to review for coreboot: veyron_*: Remove obsolete Chromeboxes
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Nov 22 14:48:52 CET 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17569
-gerrit
commit 0c668bfaf077da744eaed53cc492864308857fa8
Author: David Hendricks <dhendrix at chromium.org>
Date: Tue May 17 18:01:31 2016 -0700
veyron_*: Remove obsolete Chromeboxes
This removes brain, danger, emile, and romy from the tree.
This was cherry-picked from the chromeos-2016.02 branch (CL:345574),
but conflicts showed up in many files that were to be deleted anyway
possibly due to some widespread refactoring that was done between
then and now.
BUG=chromium:612660
BRANCH=none
TEST=none
Change-Id: Ie37140a9a4bb9d820a3fcbad6674b2fa737e1249
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 1ebe5038a82162f6345e319de7578f26ccd68b73
Original-Change-Id: I11f7e0870916871d8f146a6871370ace76ddec49
Original-Signed-off-by: David Hendricks <dhendrix at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/412424
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
src/mainboard/google/veyron_brain/Kconfig | 75 ---------
src/mainboard/google/veyron_brain/Kconfig.name | 2 -
src/mainboard/google/veyron_brain/Makefile.inc | 38 -----
src/mainboard/google/veyron_brain/board.h | 26 ---
src/mainboard/google/veyron_brain/board_info.txt | 6 -
src/mainboard/google/veyron_brain/boardid.c | 45 ------
src/mainboard/google/veyron_brain/bootblock.c | 72 ---------
src/mainboard/google/veyron_brain/chromeos.c | 61 -------
src/mainboard/google/veyron_brain/chromeos.fmd | 29 ----
src/mainboard/google/veyron_brain/devicetree.cb | 22 ---
src/mainboard/google/veyron_brain/mainboard.c | 121 --------------
src/mainboard/google/veyron_brain/memlayout.ld | 14 --
src/mainboard/google/veyron_brain/reset.c | 26 ---
src/mainboard/google/veyron_brain/romstage.c | 103 ------------
src/mainboard/google/veyron_brain/sdram_configs.c | 50 ------
.../sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 ---------
.../sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 ---------
.../google/veyron_brain/sdram_inf/sdram-unused.inc | 3 -
src/mainboard/google/veyron_danger/Kconfig | 76 ---------
src/mainboard/google/veyron_danger/Kconfig.name | 2 -
src/mainboard/google/veyron_danger/Makefile.inc | 40 -----
src/mainboard/google/veyron_danger/board.h | 30 ----
src/mainboard/google/veyron_danger/board_info.txt | 6 -
src/mainboard/google/veyron_danger/boardid.c | 48 ------
src/mainboard/google/veyron_danger/bootblock.c | 72 ---------
src/mainboard/google/veyron_danger/chromeos.c | 64 --------
src/mainboard/google/veyron_danger/chromeos.fmd | 29 ----
src/mainboard/google/veyron_danger/devicetree.cb | 22 ---
src/mainboard/google/veyron_danger/mainboard.c | 177 ---------------------
src/mainboard/google/veyron_danger/memlayout.ld | 16 --
src/mainboard/google/veyron_danger/reset.c | 26 ---
src/mainboard/google/veyron_danger/romstage.c | 107 -------------
src/mainboard/google/veyron_danger/sdmmc.c | 41 -----
src/mainboard/google/veyron_danger/sdram_configs.c | 55 -------
.../sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 ---------
.../sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 ---------
.../veyron_danger/sdram_inf/sdram-unused.inc | 3 -
src/mainboard/google/veyron_emile/Kconfig | 75 ---------
src/mainboard/google/veyron_emile/Kconfig.name | 2 -
src/mainboard/google/veyron_emile/Makefile.inc | 40 -----
src/mainboard/google/veyron_emile/board.h | 28 ----
src/mainboard/google/veyron_emile/board_info.txt | 6 -
src/mainboard/google/veyron_emile/boardid.c | 45 ------
src/mainboard/google/veyron_emile/bootblock.c | 72 ---------
src/mainboard/google/veyron_emile/chromeos.c | 58 -------
src/mainboard/google/veyron_emile/chromeos.fmd | 29 ----
src/mainboard/google/veyron_emile/devicetree.cb | 22 ---
src/mainboard/google/veyron_emile/mainboard.c | 144 -----------------
src/mainboard/google/veyron_emile/memlayout.ld | 14 --
src/mainboard/google/veyron_emile/reset.c | 26 ---
src/mainboard/google/veyron_emile/romstage.c | 106 ------------
src/mainboard/google/veyron_emile/sdmmc.c | 34 ----
src/mainboard/google/veyron_emile/sdram_configs.c | 50 ------
.../sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 ---------
.../sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 ---------
.../google/veyron_emile/sdram_inf/sdram-unused.inc | 3 -
src/mainboard/google/veyron_romy/Kconfig | 75 ---------
src/mainboard/google/veyron_romy/Kconfig.name | 2 -
src/mainboard/google/veyron_romy/Makefile.inc | 38 -----
src/mainboard/google/veyron_romy/board.h | 26 ---
src/mainboard/google/veyron_romy/board_info.txt | 6 -
src/mainboard/google/veyron_romy/boardid.c | 45 ------
src/mainboard/google/veyron_romy/bootblock.c | 72 ---------
src/mainboard/google/veyron_romy/chromeos.c | 61 -------
src/mainboard/google/veyron_romy/chromeos.fmd | 29 ----
src/mainboard/google/veyron_romy/devicetree.cb | 22 ---
src/mainboard/google/veyron_romy/mainboard.c | 114 -------------
src/mainboard/google/veyron_romy/memlayout.ld | 14 --
src/mainboard/google/veyron_romy/reset.c | 26 ---
src/mainboard/google/veyron_romy/romstage.c | 103 ------------
src/mainboard/google/veyron_romy/sdram_configs.c | 50 ------
.../veyron_romy/sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 ---------
.../veyron_romy/sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 ---------
.../veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 ---------
.../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 ---------
.../sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc | 78 ---------
.../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 ---------
.../google/veyron_romy/sdram_inf/sdram-unused.inc | 3 -
122 files changed, 7307 deletions(-)
diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig
deleted file mode 100644
index 1348f23..0000000
--- a/src/mainboard/google/veyron_brain/Kconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-if BOARD_GOOGLE_VEYRON_BRAIN
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select BOARD_ROMSIZE_KB_4096
- select COMMON_CBFS_SPI_WRAPPER
- select HAVE_HARD_RESET
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select PHYSICAL_REC_SWITCH
- select VBOOT_VBNV_FLASH
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_brain
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Brain"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config BOOT_DEVICE_SPI_FLASH_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-config GBB_HWID
- string
- depends on CHROMEOS
- default "BRAIN TEST A-A 7204"
-endif # BOARD_GOOGLE_VEYRON_BRAIN
diff --git a/src/mainboard/google/veyron_brain/Kconfig.name b/src/mainboard/google/veyron_brain/Kconfig.name
deleted file mode 100644
index 6d5694d..0000000
--- a/src/mainboard/google/veyron_brain/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_BRAIN
- bool "Veyron_Brain"
diff --git a/src/mainboard/google/veyron_brain/Makefile.inc b/src/mainboard/google/veyron_brain/Makefile.inc
deleted file mode 100644
index 0abb668..0000000
--- a/src/mainboard/google/veyron_brain/Makefile.inc
+++ /dev/null
@@ -1,38 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_brain/board.h b/src/mainboard/google/veyron_brain/board.h
deleted file mode 100644
index 155dde4..0000000
--- a/src/mainboard/google/veyron_brain/board.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_BRAIN_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_BRAIN_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_RESET GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_BRAIN_BOARD_H */
diff --git a/src/mainboard/google/veyron_brain/board_info.txt b/src/mainboard/google/veyron_brain/board_info.txt
deleted file mode 100644
index c82b566..0000000
--- a/src/mainboard/google/veyron_brain/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Google
-Board name: Veyron Brain Rockchip RK3288 chromebox
-Category: settop
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/google/veyron_brain/boardid.c b/src/mainboard/google/veyron_brain/boardid.c
deleted file mode 100644
index d0456d7..0000000
--- a/src/mainboard/google/veyron_brain/boardid.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c
deleted file mode 100644
index b95a265..0000000
--- a/src/mainboard/google/veyron_brain/bootblock.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- gpio_output(GPIO(7, A, 0), 1); /* Power LED */
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu(APLL_1800_MHZ);
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_brain/chromeos.c b/src/mainboard/google/veyron_brain/chromeos.c
deleted file mode 100644
index 1e6d35b..0000000
--- a/src/mainboard/google/veyron_brain/chromeos.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"},
- {GPIO_RECOVERY.raw, ACTIVE_LOW,
- gpio_get(GPIO_RECOVERY), "recovery"},
- {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"},
- {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
- {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"},
- };
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- return !gpio_get(GPIO_RECOVERY);
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_brain/chromeos.fmd b/src/mainboard/google/veyron_brain/chromeos.fmd
deleted file mode 100644
index 9c618e3..0000000
--- a/src/mainboard/google/veyron_brain/chromeos.fmd
+++ /dev/null
@@ -1,29 +0,0 @@
-FLASH at 0x0 0x400000 {
- WP_RO at 0x0 0x200000 {
- RO_SECTION at 0x0 0x1f0000 {
- BOOTBLOCK at 0 128K
- COREBOOT(CBFS)@0x20000 0xe0000
- FMAP at 0x100000 0x1000
- GBB at 0x101000 0xeef00
- RO_FRID at 0x1eff00 0x100
- }
- RO_VPD at 0x1f0000 0x10000
- }
- RW_SECTION_A at 0x200000 0x78000 {
- VBLOCK_A at 0x0 0x2000
- FW_MAIN_A(CBFS)@0x2000 0x75f00
- RW_FWID_A at 0x77f00 0x100
- }
- RW_SHARED at 0x278000 0x2000 {
- SHARED_DATA at 0x0 0x2000
- }
- RW_NVRAM at 0x27a000 0x2000
- RW_ELOG at 0x27c000 0x4000
- RW_SECTION_B at 0x280000 0x78000 {
- VBLOCK_B at 0x0 0x2000
- FW_MAIN_B(CBFS)@0x2000 0x75f00
- RW_FWID_B at 0x77f00 0x100
- }
- RW_VPD at 0x2f8000 0x8000
- RW_LEGACY(CBFS)@0x300000 0x100000
-}
diff --git a/src/mainboard/google/veyron_brain/devicetree.cb b/src/mainboard/google/veyron_brain/devicetree.cb
deleted file mode 100644
index b3c9a47..0000000
--- a/src/mainboard/google/veyron_brain/devicetree.cb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_HDMI"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_brain/mainboard.c b/src/mainboard/google/veyron_brain/mainboard.c
deleted file mode 100644
index cc07278..0000000
--- a/src/mainboard/google/veyron_brain/mainboard.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 4), 1); /* USB2_PWR_EN */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-}
-
-static void configure_hdmi(void)
-{
- rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */
- rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-
- /* set POWER_HDMI_ON */
- gpio_output(GPIO(7, A, 2), 1);
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_emmc();
- configure_codec();
- configure_vop();
- configure_hdmi();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- return;
-}
diff --git a/src/mainboard/google/veyron_brain/memlayout.ld b/src/mainboard/google/veyron_brain/memlayout.ld
deleted file mode 100644
index 2c33306..0000000
--- a/src/mainboard/google/veyron_brain/memlayout.ld
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_brain/reset.c b/src/mainboard/google/veyron_brain/reset.c
deleted file mode 100644
index 0d11e76..0000000
--- a/src/mainboard/google/veyron_brain/reset.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c
deleted file mode 100644
index 1c139f1..0000000
--- a/src/mainboard/google/veyron_brain/romstage.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- exception_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_brain/sdram_configs.c b/src/mainboard/google/veyron_brain/sdram_configs.c
deleted file mode 100644
index 76e4f76..0000000
--- a/src/mainboard/google/veyron_brain/sdram_configs.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b27..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc
deleted file mode 100644
index 8d22e6c..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* Hynix H9CCNNNBPTBLBR-NUD chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 1c35c90..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
deleted file mode 100644
index c4ce972..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Samsung K4E8E324EB-EGCF chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
deleted file mode 100644
index 6b6df57..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Samsung K4E6E304EB-EGCE chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 0edcb70..0000000
--- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-},
diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig
deleted file mode 100644
index ab667d8..0000000
--- a/src/mainboard/google/veyron_danger/Kconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-if BOARD_GOOGLE_VEYRON_DANGER
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select BOARD_ROMSIZE_KB_4096
- select COMMON_CBFS_SPI_WRAPPER
- select HAVE_HARD_RESET
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
-
-config CHROMEOS
- select PHYSICAL_REC_SWITCH
- select VBOOT_VBNV_FLASH
-
-config MAINBOARD_DIR
- string
- default google/veyron_danger
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Danger"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config BOOT_DEVICE_SPI_FLASH_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-config GBB_HWID
- string
- depends on CHROMEOS
- default "DANGER TEST A-A 2785"
-endif # BOARD_GOOGLE_VEYRON_DANGER
diff --git a/src/mainboard/google/veyron_danger/Kconfig.name b/src/mainboard/google/veyron_danger/Kconfig.name
deleted file mode 100644
index 8e6d070..0000000
--- a/src/mainboard/google/veyron_danger/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_DANGER
- bool "Veyron_Danger"
diff --git a/src/mainboard/google/veyron_danger/Makefile.inc b/src/mainboard/google/veyron_danger/Makefile.inc
deleted file mode 100644
index dbb7779..0000000
--- a/src/mainboard/google/veyron_danger/Makefile.inc
+++ /dev/null
@@ -1,40 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdmmc.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-ramstage-y += sdmmc.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_danger/board.h b/src/mainboard/google/veyron_danger/board.h
deleted file mode 100644
index 3456e6a..0000000
--- a/src/mainboard/google/veyron_danger/board.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_DANGER_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_DANGER_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT GPIO(7, A, 3)
-#define GPIO_RESET GPIO(0, B, 5)
-#define GPIO_LCDC_BL GPIO(7, A, 7)
-
-void sdmmc_power_off(void);
-void sdmmc_power_on(void);
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_DANGER_BOARD_H */
diff --git a/src/mainboard/google/veyron_danger/board_info.txt b/src/mainboard/google/veyron_danger/board_info.txt
deleted file mode 100644
index a2077a2..0000000
--- a/src/mainboard/google/veyron_danger/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Google
-Board name: Veyron Danger Rockchip RK3288 board
-Category: misc
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/google/veyron_danger/boardid.c b/src/mainboard/google/veyron_danger/boardid.c
deleted file mode 100644
index 9017bcb..0000000
--- a/src/mainboard/google/veyron_danger/boardid.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
-#if 0
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
-#endif
- code = 0;
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c
deleted file mode 100644
index b95a265..0000000
--- a/src/mainboard/google/veyron_danger/bootblock.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- gpio_output(GPIO(7, A, 0), 1); /* Power LED */
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu(APLL_1800_MHZ);
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_danger/chromeos.c b/src/mainboard/google/veyron_danger/chromeos.c
deleted file mode 100644
index 4166654..0000000
--- a/src/mainboard/google/veyron_danger/chromeos.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-#define GPIO_DEV_MODE GPIO(7, B, 2)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input(GPIO_POWER);
- gpio_input(GPIO_DEV_MODE);
- gpio_input_pullup(GPIO_RECOVERY);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"},
- {GPIO_RECOVERY.raw, ACTIVE_LOW,
- gpio_get(GPIO_RECOVERY), "recovery"},
- {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"},
- {GPIO_DEV_MODE.raw, ACTIVE_HIGH,
- get_developer_mode_switch(), "developer"},
- {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"},
- };
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-
-int get_developer_mode_switch(void)
-{
- return !gpio_get(GPIO_DEV_MODE);
-}
-
-int get_recovery_mode_switch(void)
-{
- return !gpio_get(GPIO_RECOVERY);
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_danger/chromeos.fmd b/src/mainboard/google/veyron_danger/chromeos.fmd
deleted file mode 100644
index 9c618e3..0000000
--- a/src/mainboard/google/veyron_danger/chromeos.fmd
+++ /dev/null
@@ -1,29 +0,0 @@
-FLASH at 0x0 0x400000 {
- WP_RO at 0x0 0x200000 {
- RO_SECTION at 0x0 0x1f0000 {
- BOOTBLOCK at 0 128K
- COREBOOT(CBFS)@0x20000 0xe0000
- FMAP at 0x100000 0x1000
- GBB at 0x101000 0xeef00
- RO_FRID at 0x1eff00 0x100
- }
- RO_VPD at 0x1f0000 0x10000
- }
- RW_SECTION_A at 0x200000 0x78000 {
- VBLOCK_A at 0x0 0x2000
- FW_MAIN_A(CBFS)@0x2000 0x75f00
- RW_FWID_A at 0x77f00 0x100
- }
- RW_SHARED at 0x278000 0x2000 {
- SHARED_DATA at 0x0 0x2000
- }
- RW_NVRAM at 0x27a000 0x2000
- RW_ELOG at 0x27c000 0x4000
- RW_SECTION_B at 0x280000 0x78000 {
- VBLOCK_B at 0x0 0x2000
- FW_MAIN_B(CBFS)@0x2000 0x75f00
- RW_FWID_B at 0x77f00 0x100
- }
- RW_VPD at 0x2f8000 0x8000
- RW_LEGACY(CBFS)@0x300000 0x100000
-}
diff --git a/src/mainboard/google/veyron_danger/devicetree.cb b/src/mainboard/google/veyron_danger/devicetree.cb
deleted file mode 100644
index 0453a1d..0000000
--- a/src/mainboard/google/veyron_danger/devicetree.cb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_AUTO_DETECT"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_danger/mainboard.c b/src/mainboard/google/veyron_danger/mainboard.c
deleted file mode 100644
index 39f0b2a..0000000
--- a/src/mainboard/google/veyron_danger/mainboard.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
- gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- sdmmc_power_on();
-
- gpio_input(GPIO(7, A, 5)); /* SDMMC_DET_L */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- /*
- * BL_EN gates VCC_LCD. This might be changed in future revisions
- * of the board so that the display can be stablized before we
- * turn on the backlight.
- *
- * To minimize display corruption, turn off LCDC_BL before
- * powering on the backlight.
- */
- switch (board_id()) {
- case 0:
- gpio_output(GPIO(7, A, 3), 1);
- break;
- default:
- gpio_output(GPIO(7, A, 2), 1);
- break;
- }
-
- gpio_output(GPIO_LCDC_BL, 0);
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-
- /* EDP_HPD setup */
- switch (board_id()) {
- case 0:
- /* not present */
- break;
- default:
- /* Unlike other Veyrons, Danger has external pull resistors on
- * EDP_HPD. Default for GPIO(7, B, 3) is pull-down, set to
- * float.
- */
- gpio_input(GPIO(7, B, 3));
- write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
- break;
- }
-}
-
-static void configure_hdmi(void)
-{
- rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */
- rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */
-
- /* set POWER_HDMI_EN */
- switch (board_id()) {
- case 0:
- gpio_output(GPIO(7, A, 2), 1);
- break;
- default:
- gpio_output(GPIO(5, C, 3), 1);
- break;
- }
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_codec();
- configure_vop();
- configure_hdmi();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- gpio_output(GPIO_LCDC_BL, 1);
-}
diff --git a/src/mainboard/google/veyron_danger/memlayout.ld b/src/mainboard/google/veyron_danger/memlayout.ld
deleted file mode 100644
index 207a5c6..0000000
--- a/src/mainboard/google/veyron_danger/memlayout.ld
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_danger/reset.c b/src/mainboard/google/veyron_danger/reset.c
deleted file mode 100644
index 0d11e76..0000000
--- a/src/mainboard/google/veyron_danger/reset.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c
deleted file mode 100644
index e320898..0000000
--- a/src/mainboard/google/veyron_danger/romstage.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- exception_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_danger/sdmmc.c b/src/mainboard/google/veyron_danger/sdmmc.c
deleted file mode 100644
index 41f2659..0000000
--- a/src/mainboard/google/veyron_danger/sdmmc.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "board.h"
-
-#include <soc/rk808.h>
-
-static void sdmmc_power(int enable)
-{
- switch (board_id()) {
- case 0:
- /* VCC33_SD is tied to VCC33_SYS and is always on */
- break;
- default:
- rk808_configure_ldo(4, enable ? 3300 : 0); /* VCC33_SD_LDO */
- rk808_configure_ldo(5, enable ? 3300 : 0); /* VCCIO_SD */
- break;
- }
-}
-
-void sdmmc_power_off(void)
-{
- sdmmc_power(0);
-}
-
-void sdmmc_power_on(void)
-{
- sdmmc_power(1);
-}
diff --git a/src/mainboard/google/veyron_danger/sdram_configs.c b/src/mainboard/google/veyron_danger/sdram_configs.c
deleted file mode 100644
index c7f2055..0000000
--- a/src/mainboard/google/veyron_danger/sdram_configs.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode;
-
- /* early boards had incorrect config */
- if (board_id() == 0)
- return &sdram_configs[0];
-
- ramcode = ram_code();
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b27..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc
deleted file mode 100644
index 8d22e6c..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* Hynix H9CCNNNBPTBLBR-NUD chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 1c35c90..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
deleted file mode 100644
index c4ce972..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Samsung K4E8E324EB-EGCF chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
deleted file mode 100644
index 6b6df57..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Samsung K4E6E304EB-EGCE chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 0edcb70..0000000
--- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-},
diff --git a/src/mainboard/google/veyron_emile/Kconfig b/src/mainboard/google/veyron_emile/Kconfig
deleted file mode 100644
index d5884f9..0000000
--- a/src/mainboard/google/veyron_emile/Kconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-if BOARD_GOOGLE_VEYRON_EMILE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select BOARD_ROMSIZE_KB_4096
- select COMMON_CBFS_SPI_WRAPPER
- select HAVE_HARD_RESET
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
- select MAINBOARD_HAS_NATIVE_VGA_INIT
-
-config CHROMEOS
- select PHYSICAL_REC_SWITCH
- select VBOOT_VBNV_FLASH
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_emile
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_emile"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config BOOT_DEVICE_SPI_FLASH_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-config GBB_HWID
- string
- depends on CHROMEOS
- default "EMILE TEST A-A 0992"
-endif # BOARD_GOOGLE_VEYRON_EMILE
diff --git a/src/mainboard/google/veyron_emile/Kconfig.name b/src/mainboard/google/veyron_emile/Kconfig.name
deleted file mode 100644
index 2ce3437..0000000
--- a/src/mainboard/google/veyron_emile/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_EMILE
- bool "Veyron_Emile"
diff --git a/src/mainboard/google/veyron_emile/Makefile.inc b/src/mainboard/google/veyron_emile/Makefile.inc
deleted file mode 100644
index dbb7779..0000000
--- a/src/mainboard/google/veyron_emile/Makefile.inc
+++ /dev/null
@@ -1,40 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdmmc.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-ramstage-y += sdmmc.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_emile/board.h b/src/mainboard/google/veyron_emile/board.h
deleted file mode 100644
index dd2a1d7..0000000
--- a/src/mainboard/google/veyron_emile/board.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_EMILE_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_EMILE_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_RESET GPIO(0, B, 5)
-
-void sdmmc_power_off(void);
-void sdmmc_power_on(void);
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_EMILE_BOARD_H */
diff --git a/src/mainboard/google/veyron_emile/board_info.txt b/src/mainboard/google/veyron_emile/board_info.txt
deleted file mode 100644
index bc7b70d..0000000
--- a/src/mainboard/google/veyron_emile/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Google
-Board name: Veyron Emile Rockchip RK3288 board
-Category: misc
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: ?
diff --git a/src/mainboard/google/veyron_emile/boardid.c b/src/mainboard/google/veyron_emile/boardid.c
deleted file mode 100644
index d0456d7..0000000
--- a/src/mainboard/google/veyron_emile/boardid.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_emile/bootblock.c b/src/mainboard/google/veyron_emile/bootblock.c
deleted file mode 100644
index 7261275..0000000
--- a/src/mainboard/google/veyron_emile/bootblock.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- gpio_output(GPIO(0, B, 3), 1); /* Power LED */
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu(APLL_1800_MHZ);
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_emile/chromeos.c b/src/mainboard/google/veyron_emile/chromeos.c
deleted file mode 100644
index 5cb9ec4..0000000
--- a/src/mainboard/google/veyron_emile/chromeos.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_RECOVERY);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"},
- {GPIO_RECOVERY.raw, ACTIVE_LOW,
- gpio_get(GPIO_RECOVERY), "recovery"},
- {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
- {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"},
- };
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- return !gpio_get(GPIO_RECOVERY);
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_emile/chromeos.fmd b/src/mainboard/google/veyron_emile/chromeos.fmd
deleted file mode 100644
index 9c618e3..0000000
--- a/src/mainboard/google/veyron_emile/chromeos.fmd
+++ /dev/null
@@ -1,29 +0,0 @@
-FLASH at 0x0 0x400000 {
- WP_RO at 0x0 0x200000 {
- RO_SECTION at 0x0 0x1f0000 {
- BOOTBLOCK at 0 128K
- COREBOOT(CBFS)@0x20000 0xe0000
- FMAP at 0x100000 0x1000
- GBB at 0x101000 0xeef00
- RO_FRID at 0x1eff00 0x100
- }
- RO_VPD at 0x1f0000 0x10000
- }
- RW_SECTION_A at 0x200000 0x78000 {
- VBLOCK_A at 0x0 0x2000
- FW_MAIN_A(CBFS)@0x2000 0x75f00
- RW_FWID_A at 0x77f00 0x100
- }
- RW_SHARED at 0x278000 0x2000 {
- SHARED_DATA at 0x0 0x2000
- }
- RW_NVRAM at 0x27a000 0x2000
- RW_ELOG at 0x27c000 0x4000
- RW_SECTION_B at 0x280000 0x78000 {
- VBLOCK_B at 0x0 0x2000
- FW_MAIN_B(CBFS)@0x2000 0x75f00
- RW_FWID_B at 0x77f00 0x100
- }
- RW_VPD at 0x2f8000 0x8000
- RW_LEGACY(CBFS)@0x300000 0x100000
-}
diff --git a/src/mainboard/google/veyron_emile/devicetree.cb b/src/mainboard/google/veyron_emile/devicetree.cb
deleted file mode 100644
index b3c9a47..0000000
--- a/src/mainboard/google/veyron_emile/devicetree.cb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_HDMI"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_emile/mainboard.c b/src/mainboard/google/veyron_emile/mainboard.c
deleted file mode 100644
index b264df9..0000000
--- a/src/mainboard/google/veyron_emile/mainboard.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void enable_5v_drv(void)
-{
- gpio_output(GPIO(7, A, 3), 1); /* 5v_drv enable */
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- sdmmc_power_on();
-
- gpio_input(GPIO(7, A, 5)); /* SDMMC_DET_L */
-}
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(2, B, 2), 1); /* USB3_PWR_EN */
- gpio_output(GPIO(2, B, 3), 1); /* USB2_PWR_EN */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_i2s(void)
-{
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- rk808_configure_ldo(8, 1800); /* VCC18_LCD (HDMI_AVDD_1V8) */
- rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-}
-
-static void configure_hdmi(void)
-{
- /* HDMI I2C */
- write32(&rk3288_grf->iomux_i2c5sda, IOMUX_HDMI_EDP_I2C_SDA);
- write32(&rk3288_grf->iomux_i2c5scl, IOMUX_HDMI_EDP_I2C_SCL);
-
- gpio_output(GPIO(7, A, 2), 1); /* POWER_HDMI_ON */
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- enable_5v_drv();
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_i2s();
- configure_vop();
- configure_hdmi();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- /* Retrieve the MAC addr which would pass to DTS. */
- lb_table_add_macs_from_vpd(header);
- }
-}
-
-void mainboard_power_on_backlight(void)
-{
- return;
-}
diff --git a/src/mainboard/google/veyron_emile/memlayout.ld b/src/mainboard/google/veyron_emile/memlayout.ld
deleted file mode 100644
index 2c33306..0000000
--- a/src/mainboard/google/veyron_emile/memlayout.ld
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_emile/reset.c b/src/mainboard/google/veyron_emile/reset.c
deleted file mode 100644
index 0d11e76..0000000
--- a/src/mainboard/google/veyron_emile/reset.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_emile/romstage.c b/src/mainboard/google/veyron_emile/romstage.c
deleted file mode 100644
index dc4fe6c..0000000
--- a/src/mainboard/google/veyron_emile/romstage.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- exception_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_emile/sdmmc.c b/src/mainboard/google/veyron_emile/sdmmc.c
deleted file mode 100644
index fe217ec..0000000
--- a/src/mainboard/google/veyron_emile/sdmmc.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "board.h"
-
-#include <soc/rk808.h>
-
-static void sdmmc_power(int enable)
-{
- rk808_configure_ldo(4, enable ? 3300 : 0); /* VCC33_SD_LDO */
- rk808_configure_ldo(5, enable ? 3300 : 0); /* VCCIO_SD */
-}
-
-void sdmmc_power_off(void)
-{
- sdmmc_power(0);
-}
-
-void sdmmc_power_on(void)
-{
- sdmmc_power(1);
-}
diff --git a/src/mainboard/google/veyron_emile/sdram_configs.c b/src/mainboard/google/veyron_emile/sdram_configs.c
deleted file mode 100644
index 76e4f76..0000000
--- a/src/mainboard/google/veyron_emile/sdram_configs.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b27..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc
deleted file mode 100644
index 8d22e6c..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* Hynix H9CCNNNBPTBLBR-NUD chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 1c35c90..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
deleted file mode 100644
index c4ce972..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Samsung K4E8E324EB-EGCF chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
deleted file mode 100644
index 6b6df57..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Samsung K4E6E304EB-EGCE chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 0edcb70..0000000
--- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-},
diff --git a/src/mainboard/google/veyron_romy/Kconfig b/src/mainboard/google/veyron_romy/Kconfig
deleted file mode 100644
index e91034e..0000000
--- a/src/mainboard/google/veyron_romy/Kconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-if BOARD_GOOGLE_VEYRON_ROMY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select BOARD_ROMSIZE_KB_4096
- select COMMON_CBFS_SPI_WRAPPER
- select HAVE_HARD_RESET
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select PHYSICAL_REC_SWITCH
- select VBOOT_VBNV_FLASH
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_romy
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Romy"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config BOOT_DEVICE_SPI_FLASH_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-config GBB_HWID
- string
- depends on CHROMEOS
- default "ROMY TEST A-A 5801"
-endif # BOARD_GOOGLE_VEYRON_ROMY
diff --git a/src/mainboard/google/veyron_romy/Kconfig.name b/src/mainboard/google/veyron_romy/Kconfig.name
deleted file mode 100644
index 5c02b7e..0000000
--- a/src/mainboard/google/veyron_romy/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_ROMY
- bool "Veyron_Romy"
diff --git a/src/mainboard/google/veyron_romy/Makefile.inc b/src/mainboard/google/veyron_romy/Makefile.inc
deleted file mode 100644
index 0abb668..0000000
--- a/src/mainboard/google/veyron_romy/Makefile.inc
+++ /dev/null
@@ -1,38 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_romy/board.h b/src/mainboard/google/veyron_romy/board.h
deleted file mode 100644
index 74e7f6f..0000000
--- a/src/mainboard/google/veyron_romy/board.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_ROMY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_ROMY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_RESET GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_ROMY_BOARD_H */
diff --git a/src/mainboard/google/veyron_romy/board_info.txt b/src/mainboard/google/veyron_romy/board_info.txt
deleted file mode 100644
index a1ae42d..0000000
--- a/src/mainboard/google/veyron_romy/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Google
-Board name: Veyron Romy Rockchip RK3288 board
-Category: misc
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: ?
diff --git a/src/mainboard/google/veyron_romy/boardid.c b/src/mainboard/google/veyron_romy/boardid.c
deleted file mode 100644
index d0456d7..0000000
--- a/src/mainboard/google/veyron_romy/boardid.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_romy/bootblock.c b/src/mainboard/google/veyron_romy/bootblock.c
deleted file mode 100644
index b95a265..0000000
--- a/src/mainboard/google/veyron_romy/bootblock.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- gpio_output(GPIO(7, A, 0), 1); /* Power LED */
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu(APLL_1800_MHZ);
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_romy/chromeos.c b/src/mainboard/google/veyron_romy/chromeos.c
deleted file mode 100644
index 1e6d35b..0000000
--- a/src/mainboard/google/veyron_romy/chromeos.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"},
- {GPIO_RECOVERY.raw, ACTIVE_LOW,
- gpio_get(GPIO_RECOVERY), "recovery"},
- {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"},
- {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
- {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"},
- };
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- return !gpio_get(GPIO_RECOVERY);
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_romy/chromeos.fmd b/src/mainboard/google/veyron_romy/chromeos.fmd
deleted file mode 100644
index fc7cf3b..0000000
--- a/src/mainboard/google/veyron_romy/chromeos.fmd
+++ /dev/null
@@ -1,29 +0,0 @@
-FLASH at 0x0 0x400000 {
- WP_RO at 0x0 0x200000 {
- RO_SECTION at 0x0 0x1f0000 {
- BOOTBLOCK at 0 128K
- COREBOOT(CBFS)@0x20000 0x160000
- FMAP at 0x180000 0x1000
- GBB at 0x181000 0x6ef00
- RO_FRID at 0x1eff00 0x100
- }
- RO_VPD at 0x1f0000 0x10000
- }
- RW_SECTION_A at 0x200000 0x78000 {
- VBLOCK_A at 0x0 0x2000
- FW_MAIN_A(CBFS)@0x2000 0x75f00
- RW_FWID_A at 0x77f00 0x100
- }
- RW_SHARED at 0x278000 0x2000 {
- SHARED_DATA at 0x0 0x2000
- }
- RW_NVRAM at 0x27a000 0x2000
- RW_ELOG at 0x27c000 0x4000
- RW_SECTION_B at 0x280000 0x78000 {
- VBLOCK_B at 0x0 0x2000
- FW_MAIN_B(CBFS)@0x2000 0x75f00
- RW_FWID_B at 0x77f00 0x100
- }
- RW_VPD at 0x2f8000 0x8000
- RW_LEGACY(CBFS)@0x300000 0x100000
-}
diff --git a/src/mainboard/google/veyron_romy/devicetree.cb b/src/mainboard/google/veyron_romy/devicetree.cb
deleted file mode 100644
index 0453a1d..0000000
--- a/src/mainboard/google/veyron_romy/devicetree.cb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_AUTO_DETECT"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_romy/mainboard.c b/src/mainboard/google/veyron_romy/mainboard.c
deleted file mode 100644
index 9f68a09..0000000
--- a/src/mainboard/google/veyron_romy/mainboard.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */
- rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_emmc();
- configure_codec();
- configure_vop();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- return;
-}
diff --git a/src/mainboard/google/veyron_romy/memlayout.ld b/src/mainboard/google/veyron_romy/memlayout.ld
deleted file mode 100644
index 2c33306..0000000
--- a/src/mainboard/google/veyron_romy/memlayout.ld
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_romy/reset.c b/src/mainboard/google/veyron_romy/reset.c
deleted file mode 100644
index 0d11e76..0000000
--- a/src/mainboard/google/veyron_romy/reset.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c
deleted file mode 100644
index 1c139f1..0000000
--- a/src/mainboard/google/veyron_romy/romstage.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- exception_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_romy/sdram_configs.c b/src/mainboard/google/veyron_romy/sdram_configs.c
deleted file mode 100644
index 76e4f76..0000000
--- a/src/mainboard/google/veyron_romy/sdram_configs.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b27..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc
deleted file mode 100644
index 8d22e6c..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* Hynix H9CCNNNBPTBLBR-NUD chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 1c35c90..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
deleted file mode 100644
index c4ce972..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Samsung K4E8E324EB-EGCF chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
deleted file mode 100644
index 6b6df57..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Samsung K4E6E304EB-EGCE chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 0edcb70..0000000
--- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-},
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