[coreboot-gerrit] Patch set updated for coreboot: soc/intel/broadwell: enumerate missing USB ports in ACPI

[Matt DeVillier (matt.devillier@gmail.com)]

Matt DeVillier (matt.devillier at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17541

-gerrit

commit 25d52d7bd629e537961f9130f15390a408969735
Author: CoolStar <coolstarorganization at gmail.com>
Date:   Sun Aug 14 13:21:24 2016 -0700

    soc/intel/broadwell: enumerate missing USB ports in ACPI
    
    Broadwell supports up to 8 USB 2.0 ports on the EHCI controller
    and up to 10 USB 2.0 ports plus 4 USB 3.0 ports on the XHCI controller.
    Add missing port names to enable addition of board-specific details
    for each utilized port (which will be added in subsequent commits).
    
    ref: Mobile 5th Generation Intel Core Processor Family I/O
    datasheet, Feb 2015, rev 004
    
    Change-Id: I9f154a6f138934a862036d7af4400d491727f4a7
    Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
 src/soc/intel/broadwell/acpi/ehci.asl |  2 ++
 src/soc/intel/broadwell/acpi/xhci.asl | 20 ++++++++++++++------
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/broadwell/acpi/ehci.asl b/src/soc/intel/broadwell/acpi/ehci.asl
index 4db5aa9..1e58e80 100644
--- a/src/soc/intel/broadwell/acpi/ehci.asl
+++ b/src/soc/intel/broadwell/acpi/ehci.asl
@@ -43,5 +43,7 @@ Device (EHCI)
 		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
 		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
 		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+		Device (PRT7) { Name (_ADR, 7) } // USB Port 6
+		Device (PRT8) { Name (_ADR, 8) } // USB Port 7
 	}
 }
diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl
index a70ded9..63ed7bd 100644
--- a/src/soc/intel/broadwell/acpi/xhci.asl
+++ b/src/soc/intel/broadwell/acpi/xhci.asl
@@ -356,11 +356,19 @@ Device (XHCI)
 		Name (_ADR, 0x00000000)
 
 		// How many are there?
-		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
-		Device (PRT2) { Name (_ADR, 2) } // USB Port 1
-		Device (PRT3) { Name (_ADR, 3) } // USB Port 2
-		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
-		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
-		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+		Device (PRT1) { Name (_ADR, 1) } // USB 2.0 Port 0
+		Device (PRT2) { Name (_ADR, 2) } // USB 2.0 Port 1
+		Device (PRT3) { Name (_ADR, 3) } // USB 2.0 Port 2
+		Device (PRT4) { Name (_ADR, 4) } // USB 2.0 Port 3
+		Device (PRT5) { Name (_ADR, 5) } // USB 2.0 Port 4
+		Device (PRT6) { Name (_ADR, 6) } // USB 2.0 Port 5
+		Device (PRT7) { Name (_ADR, 7) } // USB 2.0 Port 6
+		Device (PRT8) { Name (_ADR, 8) } // USB 2.0 Port 7
+		Device (PRT9) { Name (_ADR, 9) } // USB 2.0 Port 8
+		Device (PRTA) { Name (_ADR, 10) } // USB 2.0 Port 9
+		Device (SSP1) { Name (_ADR, 11) } // USB 3.0 Port 0
+		Device (SSP2) { Name (_ADR, 12) } // USB 3.0 Port 1
+		Device (SSP3) { Name (_ADR, 13) } // USB 3.0 Port 2
+		Device (SSP4) { Name (_ADR, 14) } // USB 3.0 Port 3
 	}
 }