[coreboot-gerrit] Patch set updated for coreboot: vendorcode/skykabylake: Update header to fsp v1.4.0
Naresh Solanki (naresh.solanki@intel.com)
gerrit at coreboot.org
Tue Nov 22 05:51:14 CET 2016
Naresh Solanki (naresh.solanki at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17556
-gerrit
commit c3cb1f1f7b99497a6a030d6253b9e6e7c76dccd2
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date: Wed Nov 16 21:40:13 2016 +0530
vendorcode/skykabylake: Update header to fsp v1.4.0
Add header files as is from FSP build output without any adaptations.
Change-Id: Ic4b33c42efe8c9dbe9f9e2b11bf6344c9487d86e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
.../intel/fsp/fsp2_0/skykabylake/FspUpd.h | 4 +-
.../intel/fsp/fsp2_0/skykabylake/FspmUpd.h | 357 +++++++++--------
.../intel/fsp/fsp2_0/skykabylake/FspsUpd.h | 427 +++++++++++----------
3 files changed, 422 insertions(+), 366 deletions(-)
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h
index 8993a00..4981f21 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h
@@ -35,7 +35,7 @@ are permitted provided that the following conditions are met:
#include <FspEas.h>
-#pragma pack(push, 1)
+#pragma pack(1)
#define FSPT_UPD_SIGNATURE 0x545F4450554C424B /* 'KBLUPD_T' */
@@ -43,6 +43,6 @@ are permitted provided that the following conditions are met:
#define FSPS_UPD_SIGNATURE 0x535F4450554C424B /* 'KBLUPD_S' */
-#pragma pack(pop)
+#pragma pack()
#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
index d3e5dc6..3e65f0a 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
@@ -35,7 +35,7 @@ are permitted provided that the following conditions are met:
#include <FspUpd.h>
-#pragma pack(push, 1)
+#pragma pack(1)
///
@@ -46,7 +46,7 @@ typedef struct {
UINT8 Rsvd[3];
UINT16 MeChipInitCrc;
UINT16 BiosChipInitCrc;
-} CHIPSET_INIT_INFO;
+} SI_CHIPSET_INIT_INFO;
/** Fsp M Configuration
@@ -142,7 +142,7 @@ typedef struct {
/** Offset 0x0096
**/
- UINT16 UnusedUpdSpace0;
+ UINT8 UnusedUpdSpace0[2];
/** Offset 0x0098 - Intel Enhanced Debug
Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied
@@ -170,7 +170,7 @@ typedef struct {
/** Offset 0x00A3
**/
- UINT16 UnusedUpdSpace1;
+ UINT8 UnusedUpdSpace1[2];
/** Offset 0x00A5 - Enable SMBus
Enable/disable SMBus controller.
@@ -271,8 +271,9 @@ typedef struct {
/** Offset 0x0178 - Memory Voltage
Memory Voltage Override (Vddq). Default = no override
- 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
- Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
+ 0:Default, 1100:1.10 Volts, 1150:1.15 Volts, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30
+ Volts, 1350:1.35 Volts, 1400:1.40 Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55
+ Volts, 1600:1.60 Volts, 1650:1.65 Volts
**/
UINT16 VddVoltage;
@@ -300,21 +301,21 @@ typedef struct {
**/
UINT8 tCL;
-/** Offset 0x017E - tCWL
- Min CAS Write Latency Delay Time, 0: AUTO, max: 20
-**/
- UINT8 tCWL;
-
-/** Offset 0x017F - tFAW
+/** Offset 0x017E - tFAW
Min Four Activate Window Delay Time, 0: AUTO, max: 63
**/
UINT16 tFAW;
-/** Offset 0x0181 - tRAS
+/** Offset 0x0180 - tRAS
RAS Active Time, 0: AUTO, max: 64
**/
UINT16 tRAS;
+/** Offset 0x0182 - tCWL
+ Min CAS Write Latency Delay Time, 0: AUTO, max: 20
+**/
+ UINT8 tCWL;
+
/** Offset 0x0183 - tRCD/tRP
RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63
**/
@@ -377,31 +378,37 @@ typedef struct {
**/
UINT8 DllBwEn3;
-/** Offset 0x0191
+/** Offset 0x0191 - Command Tristate Support
+ Enable/Disable Command Tristate; <b>0: Enable</b>; 1: Disable.
+ $EN_DIS
**/
- UINT8 UnusedUpdSpace5[15];
+ UINT8 CmdTriStateDis;
-/** Offset 0x01A0 - HECI Timeouts
- Enable/Disable. 0: Disable, disable timeout check for HECI, 1: enable
- $EN_DIS
+/** Offset 0x0192
**/
- UINT8 HeciTimeouts;
+ UINT8 UnusedUpdSpace5[14];
-/** Offset 0x01A1 - HECI1 BAR address
+/** Offset 0x01A0 - HECI1 BAR address
BAR address of HECI1
**/
UINT32 Heci1BarAddress;
-/** Offset 0x01A5 - HECI2 BAR address
+/** Offset 0x01A4 - HECI2 BAR address
BAR address of HECI2
**/
UINT32 Heci2BarAddress;
-/** Offset 0x01A9 - HECI3 BAR address
+/** Offset 0x01A8 - HECI3 BAR address
BAR address of HECI3
**/
UINT32 Heci3BarAddress;
+/** Offset 0x01AC - HECI Timeouts
+ Enable/Disable. 0: Disable, disable timeout check for HECI, 1: enable
+ $EN_DIS
+**/
+ UINT8 HeciTimeouts;
+
/** Offset 0x01AD
**/
UINT8 UnusedUpdSpace6[115];
@@ -550,57 +557,57 @@ typedef struct {
**/
UINT8 DmiGen3RxCtlePeaking[2];
-/** Offset 0x0243 - PEG Gen3 RxCTLEp per-Bundle control
+/** Offset 0x0243 - DeEmphasis control for DMI
+ DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
+ 0: -6dB, 1: -3.5dB
+**/
+ UINT8 DmiDeEmphasis;
+
+/** Offset 0x0244 - PEG Gen3 RxCTLEp per-Bundle control
Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
**/
UINT8 PegGen3RxCtlePeaking[8];
-/** Offset 0x024B - Memory data pointer for saved preset search results
+/** Offset 0x024C - Memory data pointer for saved preset search results
The reference code will store the Gen3 Preset Search results in the SaDataHob's
PegData structure (SA_PEG_DATA) and platform code can save/restore this data to
skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0
**/
UINT32 PegDataPtr;
-/** Offset 0x024F - PEG PERST# GPIO information
+/** Offset 0x0250 - PEG PERST# GPIO information
The reference code will use the information in this structure in order to reset
PCIe Gen3 devices during equalization, if necessary
**/
UINT8 PegGpioData[16];
-/** Offset 0x025F
+/** Offset 0x0260
**/
- UINT8 UnusedUpdSpace7;
-
-/** Offset 0x0260 - DeEmphasis control for DMI
- DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
- 0: -6dB, 1: -3.5dB
-**/
- UINT8 DmiDeEmphasis;
+ UINT8 UnusedUpdSpace7[1];
/** Offset 0x0261 - PCIe Hot Plug Enable/Disable per port
0(Default): Disable, 1: Enable
**/
UINT8 PegRootPortHPE[3];
-/** Offset 0x0264 - Selection of the primary display device
- 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics
- 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics
-**/
- UINT8 PrimaryDisplay;
-
-/** Offset 0x0265 - Temporary MMIO address for GTTMMADR
+/** Offset 0x0264 - Temporary MMIO address for GTTMMADR
The reference code will use the information in this structure in order to reset
PCIe Gen3 devices during equalization, if necessary
**/
UINT32 GttMmAdr;
-/** Offset 0x0269 - Selection of iGFX GTT Memory size
+/** Offset 0x0268 - Selection of iGFX GTT Memory size
1=2MB, 2=4MB, 3=8MB, Default is 3
1:2MB, 2:4MB, 3:8MB
**/
UINT16 GttSize;
+/** Offset 0x026A - Selection of the primary display device
+ 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics
+ 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics
+**/
+ UINT8 PrimaryDisplay;
+
/** Offset 0x026B - Switchable Graphics GPIO information for PEG 0
Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
**/
@@ -715,8 +722,8 @@ typedef struct {
/** Offset 0x02CC - C6DRAM power gating feature
This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
- power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
- feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
+ power gating feature.- <b>0: Don't allocate any PRMRR memory for C6DRAM power gating
+ feature</b>.- 1: Allocate PRMRR memory for C6DRAM power gating feature.
$EN_DIS
**/
UINT8 EnableC6Dram;
@@ -817,39 +824,39 @@ typedef struct {
**/
UINT8 Avx2RatioOffset;
-/** Offset 0x02DC - BCLK Adaptive Voltage Enable
- When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
- Disable;<b> 1: Enable
- $EN_DIS
-**/
- UINT8 BclkAdaptiveVoltage;
-
-/** Offset 0x02DD - core voltage override
+/** Offset 0x02DC - core voltage override
The core voltage override which is applied to the entire range of cpu core frequencies.
Valid Range 0 to 2000
0x0:0xFFFF
**/
UINT16 CoreVoltageOverride;
-/** Offset 0x02DF - Core Turbo voltage Adaptive
+/** Offset 0x02DE - Core Turbo voltage Adaptive
Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
Valid Range 0 to 2000
0x0:0xFFFF
**/
UINT16 CoreVoltageAdaptive;
-/** Offset 0x02E1 - Core Turbo voltage Offset
+/** Offset 0x02E0 - Core Turbo voltage Offset
The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
0x0:0xFFFF
**/
UINT16 CoreVoltageOffset;
-/** Offset 0x02E3 - Core PLL voltage offset
+/** Offset 0x02E2 - Core PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
0x0:0xFFFF
**/
UINT16 CorePllVoltageOffset;
+/** Offset 0x02E4 - BCLK Adaptive Voltage Enable
+ When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
+ Disable;<b> 1: Enable
+ $EN_DIS
+**/
+ UINT8 BclkAdaptiveVoltage;
+
/** Offset 0x02E5 - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
$EN_DIS
@@ -868,37 +875,37 @@ typedef struct {
**/
UINT8 Txt;
-/** Offset 0x02E8 - FlashWearOutProtection
- Enable/Disable. 0: Disable, Enable/Disable FlashWearOutProtection feature, 1: enable
- $EN_DIS
-**/
- UINT8 FlashWearOutProtection;
-
-/** Offset 0x02E9 - PrmrrSize
+/** Offset 0x02E8 - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
**/
UINT32 PrmrrSize;
-/** Offset 0x02ED - SinitMemorySize
+/** Offset 0x02EC - SinitMemorySize
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
**/
UINT32 SinitMemorySize;
-/** Offset 0x02F1 - TxtHeapMemorySize
- Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
-**/
- UINT32 TxtHeapMemorySize;
-
-/** Offset 0x02F5 - TxtDprMemoryBase
+/** Offset 0x02F0 - TxtDprMemoryBase
Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
**/
UINT64 TxtDprMemoryBase;
-/** Offset 0x02FD - TxtDprMemorySize
+/** Offset 0x02F8 - TxtDprMemorySize
Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
**/
UINT32 TxtDprMemorySize;
+/** Offset 0x02FC - TxtHeapMemorySize
+ Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
+**/
+ UINT32 TxtHeapMemorySize;
+
+/** Offset 0x0300 - FlashWearOutProtection
+ Enable/Disable. 0: Disable, Enable/Disable FlashWearOutProtection feature, 1: enable
+ $EN_DIS
+**/
+ UINT8 FlashWearOutProtection;
+
/** Offset 0x0301 - ReservedSecurityPreMem
Reserved for Security Pre-Mem
$EN_DIS
@@ -917,26 +924,26 @@ typedef struct {
**/
UINT8 PchHpetBdfValid;
-/** Offset 0x030C - PCH HPET Bus Number
+/** Offset 0x030C - The HPET Base Address
+ The HPET base address. Default is 0xFED00000.
+**/
+ UINT32 PchHpetBase;
+
+/** Offset 0x0310 - PCH HPET Bus Number
Bus Number HPETn used as Requestor / Completer ID. Default is 0xF0.
**/
UINT8 PchHpetBusNumber;
-/** Offset 0x030D - PCH HPET Device Number
+/** Offset 0x0311 - PCH HPET Device Number
Device Number HPETn used as Requestor / Completer ID. Default is 0x1F.
**/
UINT8 PchHpetDeviceNumber;
-/** Offset 0x030E - PCH HPET Function Number
+/** Offset 0x0312 - PCH HPET Function Number
Function Number HPETn used as Requestor / Completer ID. Default is 0x00.
**/
UINT8 PchHpetFunctionNumber;
-/** Offset 0x030F - The HPET Base Address
- The HPET base address. Default is 0xFED00000.
-**/
- UINT32 PchHpetBase;
-
/** Offset 0x0313 - Enable PCH HSIO PCIE Rx Set Ctle
Enable PCH PCIe Gen 3 Set CTLE Value.
**/
@@ -1130,105 +1137,121 @@ typedef struct {
**/
UINT8 PchNumRsvdSmbusAddresses;
-/** Offset 0x04FB - Point of RsvdSmbusAddressTable
+/** Offset 0x04FB
+**/
+ UINT8 UnusedUpdSpace8;
+
+/** Offset 0x04FC - Point of RsvdSmbusAddressTable
Array of addresses reserved for non-ARP-capable SMBus devices.
**/
UINT32 RsvdSmbusAddressTablePtr;
-/** Offset 0x04FF - Trace Hub Memory Region 0
+/** Offset 0x0500 - Trace Hub Memory Region 0
Trace Hub Memory Region 0.
**/
UINT32 TraceHubMemReg0Size;
-/** Offset 0x0503 - Trace Hub Memory Region 1
+/** Offset 0x0504 - Trace Hub Memory Region 1
Trace Hub Memory Region 1.
**/
UINT32 TraceHubMemReg1Size;
-/** Offset 0x0507 - Enable PCIE RP Mask
+/** Offset 0x0508 - Enable PCIE RP Mask
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
for port1, bit1 for port2, and so on.
**/
UINT32 PcieRpEnableMask;
-/** Offset 0x050B - SerialIo Uart Debug
+/** Offset 0x050C - SerialIo Uart Debug
Enable SerialIo Uart debug.
0:Disable, 1:Enable
**/
UINT8 PcdSerialDebugEnable;
-/** Offset 0x050C - SerialIo Uart Number Selection
+/** Offset 0x050D - SerialIo Uart Number Selection
Select SerialIo Uart Controller for debug.
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
**/
UINT8 PcdSerialIoUartNumber;
-/** Offset 0x050D
+/** Offset 0x050E - ISA Serial Base selection
+ Select ISA Serial Base address.
+ 0(Default):0x3F8, 1:0x2F8
**/
- UINT8 ReservedFspmUpd[34];
+ UINT8 PcdIsaSerialUartBase;
+
+/** Offset 0x050F - PCH Pm Pcie Pll Ssc
+ Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
+ BIOS override.
+**/
+ UINT8 PchPmPciePllSsc;
+
+/** Offset 0x0510
+**/
+ UINT8 ReservedFspmUpd[16];
} FSP_M_CONFIG;
/** Fsp M Test Configuration
**/
typedef struct {
-/** Offset 0x052F
+/** Offset 0x0520
**/
UINT32 Signature;
-/** Offset 0x0533 - Skip external display device scanning
+/** Offset 0x0524 - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
display devices
$EN_DIS
**/
UINT8 SkipExtGfxScan;
-/** Offset 0x0534 - Generate BIOS Data ACPI Table
+/** Offset 0x0525 - Generate BIOS Data ACPI Table
Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
$EN_DIS
**/
UINT8 BdatEnable;
-/** Offset 0x0535 - Detect External Graphics device for LegacyOpROM
+/** Offset 0x0526 - Detect External Graphics device for LegacyOpROM
Detect and report if external graphics device only support LegacyOpROM or not (to
support CSM auto-enable). Enable(Default)=1, Disable=0
$EN_DIS
**/
UINT8 ScanExtGfxForLegacyOpRom;
-/** Offset 0x0536 - Lock PCU Thermal Management registers
+/** Offset 0x0527 - Lock PCU Thermal Management registers
Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
$EN_DIS
**/
UINT8 LockPTMregs;
-/** Offset 0x0537 - Enable/Disable DmiVc1
+/** Offset 0x0528 - Enable/Disable DmiVc1
Enable/Disable DmiVc1. Enable = 1, Disable (Default) = 0
$EN_DIS
**/
UINT8 DmiVc1;
-/** Offset 0x0538 - Enable/Disable DmiVcm
+/** Offset 0x0529 - Enable/Disable DmiVcm
Enable/Disable DmiVcm. Enable (Default) = 1, Disable = 0
$EN_DIS
**/
UINT8 DmiVcm;
-/** Offset 0x0539 - DMI Max Link Speed
+/** Offset 0x052A - DMI Max Link Speed
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
**/
UINT8 DmiMaxLinkSpeed;
-/** Offset 0x053A - DMI Equalization Phase 2
+/** Offset 0x052B - DMI Equalization Phase 2
DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
AUTO - Use the current default method
0:Disable phase2, 1:Enable phase2, 2:Auto
**/
UINT8 DmiGen3EqPh2Enable;
-/** Offset 0x053B - DMI Gen3 Equalization Phase3
+/** Offset 0x052C - DMI Gen3 Equalization Phase3
DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
@@ -1238,28 +1261,28 @@ typedef struct {
**/
UINT8 DmiGen3EqPh3Method;
-/** Offset 0x053C - Phase2 EQ enable on the PEG 0:1:0.
+/** Offset 0x052D - Phase2 EQ enable on the PEG 0:1:0.
Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
Enable phase 2, Auto(0x2)(Default): Use the current default method
0:Disable, 1:Enable, 2:Auto
**/
UINT8 Peg0Gen3EqPh2Enable;
-/** Offset 0x053D - Phase2 EQ enable on the PEG 0:1:1.
+/** Offset 0x052E - Phase2 EQ enable on the PEG 0:1:1.
Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
Enable phase 2, Auto(0x2)(Default): Use the current default method
0:Disable, 1:Enable, 2:Auto
**/
UINT8 Peg1Gen3EqPh2Enable;
-/** Offset 0x053E - Phase2 EQ enable on the PEG 0:1:2.
+/** Offset 0x052F - Phase2 EQ enable on the PEG 0:1:2.
Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
Enable phase 2, Auto(0x2)(Default): Use the current default method
0:Disable, 1:Enable, 2:Auto
**/
UINT8 Peg2Gen3EqPh2Enable;
-/** Offset 0x053F - Phase3 EQ method on the PEG 0:1:0.
+/** Offset 0x0530 - Phase3 EQ method on the PEG 0:1:0.
PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
@@ -1269,7 +1292,7 @@ typedef struct {
**/
UINT8 Peg0Gen3EqPh3Method;
-/** Offset 0x0540 - Phase3 EQ method on the PEG 0:1:1.
+/** Offset 0x0531 - Phase3 EQ method on the PEG 0:1:1.
PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
@@ -1279,7 +1302,7 @@ typedef struct {
**/
UINT8 Peg1Gen3EqPh3Method;
-/** Offset 0x0541 - Phase3 EQ method on the PEG 0:1:2.
+/** Offset 0x0532 - Phase3 EQ method on the PEG 0:1:2.
PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
@@ -1289,14 +1312,14 @@ typedef struct {
**/
UINT8 Peg2Gen3EqPh3Method;
-/** Offset 0x0542 - Enable/Disable PEG GEN3 Static EQ Phase1 programming
+/** Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming
Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
$EN_DIS
**/
UINT8 PegGen3ProgramStaticEq;
-/** Offset 0x0543 - PEG Gen3 SwEq Always Attempt
+/** Offset 0x0534 - PEG Gen3 SwEq Always Attempt
Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default):
Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test
and generate new EQ values every boot, not recommended
@@ -1304,7 +1327,7 @@ typedef struct {
**/
UINT8 Gen3SwEqAlwaysAttempt;
-/** Offset 0x0544 - Select number of TxEq presets to test in the PCIe/DMI SwEq
+/** Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq
Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test
Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the
current default method (Default)Auto will test Presets 7, 3, and 5. It is possible
@@ -1314,7 +1337,7 @@ typedef struct {
**/
UINT8 Gen3SwEqNumberOfPresets;
-/** Offset 0x0545 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq
+/** Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq
Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization
Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default):
Use the current default
@@ -1322,7 +1345,7 @@ typedef struct {
**/
UINT8 Gen3SwEqEnableVocTest;
-/** Offset 0x0546 - PPCIe Rx Compliance Testing Mode
+/** Offset 0x0537 - PPCIe Rx Compliance Testing Mode
Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1):
PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode;
it should only be set when doing PCIe compliance testing
@@ -1330,12 +1353,12 @@ typedef struct {
**/
UINT8 PegRxCemTestingMode;
-/** Offset 0x0547 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled
+/** Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled
the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0
**/
UINT8 PegRxCemLoopbackLane;
-/** Offset 0x0548 - Generate PCIe BDAT Margin Table
+/** Offset 0x0539 - Generate PCIe BDAT Margin Table
Set this policy to enable the generation and addition of PCIe margin data to the
BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin
data generation, Enable(0x1): Generate PCIe BDAT margin data
@@ -1343,7 +1366,11 @@ typedef struct {
**/
UINT8 PegGenerateBdatMarginTable;
-/** Offset 0x0549 - PCIe Non-Protocol Awareness for Rx Compliance Testing
+/** Offset 0x053A
+**/
+ UINT8 UnusedUpdSpace9[6];
+
+/** Offset 0x0540 - PCIe Non-Protocol Awareness for Rx Compliance Testing
Set this policy to enable the generation and addition of PCIe margin data to the
BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness,
Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for
@@ -1352,7 +1379,7 @@ typedef struct {
**/
UINT8 PegRxCemNonProtocolAwareness;
-/** Offset 0x054A - PCIe Override RxCTLE
+/** Offset 0x0541 - PCIe Override RxCTLE
Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
peak values unmodified
@@ -1360,7 +1387,7 @@ typedef struct {
**/
UINT8 PegGen3RxCtleOverride;
-/** Offset 0x054B - Rsvd
+/** Offset 0x0542 - Rsvd
Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
peak values unmodified
@@ -1368,192 +1395,192 @@ typedef struct {
**/
UINT8 PegGen3Rsvd;
-/** Offset 0x054C - PEG Gen3 Root port preset values per lane
+/** Offset 0x0543 - Panel Power Enable
+ Control for enabling/disabling VDD force bit (Required only for early enabling of
+ eDP panel). 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 PanelPowerEnable;
+
+/** Offset 0x0544 - PEG Gen3 Root port preset values per lane
Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
**/
UINT8 PegGen3RootPortPreset[16];
-/** Offset 0x055C - PEG Gen3 End port preset values per lane
+/** Offset 0x0554 - PEG Gen3 End port preset values per lane
Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
**/
UINT8 PegGen3EndPointPreset[16];
-/** Offset 0x056C - PEG Gen3 End port Hint values per lane
+/** Offset 0x0564 - PEG Gen3 End port Hint values per lane
Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
**/
UINT8 PegGen3EndPointHint[16];
-/** Offset 0x057C - Jitter Dwell Time for PCIe Gen3 Software Equalization
+/** Offset 0x0574 - Jitter Dwell Time for PCIe Gen3 Software Equalization
Range: 0-65535, default is 1000. @warning Do not change from the default
**/
UINT16 Gen3SwEqJitterDwellTime;
-/** Offset 0x057E - Jitter Error Target for PCIe Gen3 Software Equalization
+/** Offset 0x0576 - Jitter Error Target for PCIe Gen3 Software Equalization
Range: 0-65535, default is 1. @warning Do not change from the default
**/
UINT16 Gen3SwEqJitterErrorTarget;
-/** Offset 0x0580 - VOC Dwell Time for PCIe Gen3 Software Equalization
+/** Offset 0x0578 - VOC Dwell Time for PCIe Gen3 Software Equalization
Range: 0-65535, default is 10000. @warning Do not change from the default
**/
UINT16 Gen3SwEqVocDwellTime;
-/** Offset 0x0582 - VOC Error Target for PCIe Gen3 Software Equalization
+/** Offset 0x057A - VOC Error Target for PCIe Gen3 Software Equalization
Range: 0-65535, default is 2. @warning Do not change from the default
**/
UINT16 Gen3SwEqVocErrorTarget;
-/** Offset 0x0584 - Panel Power Enable
- Control for enabling/disabling VDD force bit (Required only for early enabling of
- eDP panel). 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 PanelPowerEnable;
-
-/** Offset 0x0585 - SaPreMemTestRsvd
+/** Offset 0x057C - SaPreMemTestRsvd
Reserved for SA Pre-Mem Test
$EN_DIS
**/
- UINT8 SaPreMemTestRsvd[16];
+ UINT8 SaPreMemTestRsvd[4];
-/** Offset 0x0595 - TotalFlashSize
- Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
-**/
- UINT16 TotalFlashSize;
-
-/** Offset 0x0597 - BiosSize
- Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable
-**/
- UINT16 BiosSize;
-
-/** Offset 0x0599 - BiosAcmBase
+/** Offset 0x0580 - BiosAcmBase
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
**/
UINT64 BiosAcmBase;
-/** Offset 0x05A1 - BiosAcmSize
+/** Offset 0x0588 - BiosAcmSize
Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
**/
UINT32 BiosAcmSize;
-/** Offset 0x05A5 - TgaSize
+/** Offset 0x058C - TgaSize
Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
**/
UINT32 TgaSize;
-/** Offset 0x05A9 - TxtLcpPdBase
+/** Offset 0x0590 - TxtLcpPdBase
Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
**/
UINT64 TxtLcpPdBase;
-/** Offset 0x05B1 - TxtLcpPdSize
+/** Offset 0x0598 - TxtLcpPdSize
Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
**/
UINT64 TxtLcpPdSize;
-/** Offset 0x05B9 - PCH Dci Enable
+/** Offset 0x05A0 - TotalFlashSize
+ Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
+**/
+ UINT16 TotalFlashSize;
+
+/** Offset 0x05A2 - BiosSize
+ Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable
+**/
+ UINT16 BiosSize;
+
+/** Offset 0x05A4 - PCH Dci Enable
Enable/disable PCH Dci.
$EN_DIS
**/
UINT8 PchDciEn;
-/** Offset 0x05BA - PCH Dci Auto Detect
+/** Offset 0x05A5 - PCH Dci Auto Detect
Enable/disable PCH Dci AUTO mode.
$EN_DIS
**/
UINT8 PchDciAutoDetect;
-/** Offset 0x05BB - Smbus dynamic power gating
+/** Offset 0x05A6 - Smbus dynamic power gating
Disable or Enable Smbus dynamic power gating.
$EN_DIS
**/
UINT8 SmbusDynamicPowerGating;
-/** Offset 0x05BC - Disable and Lock Watch Dog Register
+/** Offset 0x05A7 - Disable and Lock Watch Dog Register
Set 1 to clear WDT status, then disable and lock WDT registers.
$EN_DIS
**/
UINT8 WdtDisableAndLock;
-/** Offset 0x05BD - SMBUS SPD Write Disable
+/** Offset 0x05A8 - SMBUS SPD Write Disable
Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
Disable bit. For security recommendations, SPD write disable bit must be set.
$EN_DIS
**/
UINT8 SmbusSpdWriteDisable;
-/** Offset 0x05BE - ChipsetInit HECI message
+/** Offset 0x05A9 - ChipsetInit HECI message
Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message.
If disabled, it prevents from sending ChipsetInit HECI message.
$EN_DIS
**/
UINT8 ChipsetInitMessage;
-/** Offset 0x05BF - Bypass ChipsetInit sync reset.
+/** Offset 0x05AA - Bypass ChipsetInit sync reset.
0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message.
$EN_DIS
**/
UINT8 BypassPhySyncReset;
-/** Offset 0x05C0 - Force ME DID Init Status
+/** Offset 0x05AB - Force ME DID Init Status
Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, 4:
Memory not preserved across reset, Set ME DID init stat value
$EN_DIS
**/
UINT8 DidInitStat;
-/** Offset 0x05C1 - CPU Replaced Polling Disable
+/** Offset 0x05AC - CPU Replaced Polling Disable
Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
$EN_DIS
**/
UINT8 DisableCpuReplacedPolling;
-/** Offset 0x05C2 - ME DID Message
+/** Offset 0x05AD - ME DID Message
Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent
the DID message from being sent)
$EN_DIS
**/
UINT8 SendDidMsg;
-/** Offset 0x05C3 - Retry mechanism for HECI APIs
+/** Offset 0x05AE - Retry mechanism for HECI APIs
Test, 0: disable, 1: enable, Enable/Disable HECI retry.
$EN_DIS
**/
UINT8 DisableHeciRetry;
-/** Offset 0x05C4 - Check HECI message before send
+/** Offset 0x05AF - Check HECI message before send
Test, 0: disable, 1: enable, Enable/Disable message check.
$EN_DIS
**/
UINT8 DisableMessageCheck;
-/** Offset 0x05C5 - Skip MBP HOB
+/** Offset 0x05B0 - Skip MBP HOB
Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
$EN_DIS
**/
UINT8 SkipMbpHob;
-/** Offset 0x05C6 - HECI2 Interface Communication
+/** Offset 0x05B1 - HECI2 Interface Communication
Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
$EN_DIS
**/
UINT8 HeciCommunication2;
-/** Offset 0x05C7 - Enable KT device
+/** Offset 0x05B2 - Enable KT device
Test, 0: disable, 1: enable, Enable or Disable KT device.
$EN_DIS
**/
UINT8 KtDeviceEnable;
-/** Offset 0x05C8 - Enable IDEr
+/** Offset 0x05B3 - Enable IDEr
Test, 0: disable, 1: enable, Enable or Disable IDEr.
$EN_DIS
**/
UINT8 IderDeviceEnable;
-/** Offset 0x05C9
+/** Offset 0x05B4
**/
- UINT8 ReservedFspmTestUpd[17];
+ UINT8 ReservedFspmTestUpd[12];
} FSP_M_TEST_CONFIG;
/** Fsp M UPD Configuration
@@ -1572,19 +1599,19 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x052F
+/** Offset 0x0520
**/
FSP_M_TEST_CONFIG FspmTestConfig;
-/** Offset 0x05DA
+/** Offset 0x05C0
**/
- UINT8 UnusedUpdSpace8[156];
+ UINT8 UnusedUpdSpace10[134];
-/** Offset 0x0676
+/** Offset 0x0646
**/
UINT16 UpdTerminator;
} FSPM_UPD;
-#pragma pack(pop)
+#pragma pack()
#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
index 3748345..0120cf8 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
@@ -35,7 +35,7 @@ are permitted provided that the following conditions are met:
#include <FspUpd.h>
-#pragma pack(push, 1)
+#pragma pack(1)
#include <ConfigBlock/CpuConfigFspData.h>
@@ -170,7 +170,7 @@ typedef struct {
/** Offset 0x0036
**/
- UINT16 UnusedUpdSpace0;
+ UINT8 UnusedUpdSpace0[2];
/** Offset 0x0038 - MicrocodeRegionBase
Memory Base of Microcode Updates
@@ -232,25 +232,25 @@ typedef struct {
/** Offset 0x006E
**/
- UINT8 UnusedUpdSpace1[1];
+ UINT8 UnusedUpdSpace1;
-/** Offset 0x006F - Enable SerialIo Device Mode
- 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable
- SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode
- respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
+/** Offset 0x006F - Number of DevIntConfig Entry
+ Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
+ must not be NULL.
**/
- UINT8 SerialIoDevMode[11];
+ UINT8 NumOfDevIntConfig;
-/** Offset 0x007A - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
+/** Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
**/
UINT32 DevIntConfigPtr;
-/** Offset 0x007E - Number of DevIntConfig Entry
- Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
- must not be NULL.
+/** Offset 0x0074 - Enable SerialIo Device Mode
+ 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable
+ SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode
+ respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
**/
- UINT8 NumOfDevIntConfig;
+ UINT8 SerialIoDevMode[11];
/** Offset 0x007F - PIRQx to IRQx Map Config
PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
@@ -425,72 +425,72 @@ typedef struct {
**/
UINT8 FwProgress;
-/** Offset 0x0158 - SOL Switch
- Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx
- $EN_DIS
-**/
- UINT8 AmtSolEnabled;
-
-/** Offset 0x0159 - OS Timer
+/** Offset 0x0158 - OS Timer
16 bits Value, Set OS watchdog timer.
$EN_DIS
**/
UINT16 WatchDogTimerOs;
-/** Offset 0x015B - BIOS Timer
+/** Offset 0x015A - BIOS Timer
16 bits Value, Set BIOS watchdog timer.
$EN_DIS
**/
UINT16 WatchDogTimerBios;
-/** Offset 0x015D
+/** Offset 0x015C - SOL Switch
+ Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx
+ $EN_DIS
**/
- UINT8 UnusedUpdSpace6[163];
+ UINT8 AmtSolEnabled;
-/** Offset 0x0200 - Enable/Disable SA CRID
- Enable: SA CRID, Disable (Default): SA CRID
- $EN_DIS
+/** Offset 0x015D
**/
- UINT8 CridEnable;
+ UINT8 UnusedUpdSpace6[163];
-/** Offset 0x0201 - Subsystem Vendor ID for SA devices
+/** Offset 0x0200 - Subsystem Vendor ID for SA devices
Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086
**/
UINT16 DefaultSvid;
-/** Offset 0x0203 - Subsystem Device ID for SA devices
+/** Offset 0x0202 - Subsystem Device ID for SA devices
Subsystem ID that will be programmed to SA devices: Default SubSystemId=0x2015
**/
UINT16 DefaultSid;
+/** Offset 0x0204 - Enable/Disable SA CRID
+ Enable: SA CRID, Disable (Default): SA CRID
+ $EN_DIS
+**/
+ UINT8 CridEnable;
+
/** Offset 0x0205 - DMI ASPM
0=Disable, 2(Default)=L1
0:Disable, 2:L1
**/
UINT8 DmiAspm;
-/** Offset 0x0206 - PCIe DeEmphasis control per root port
+/** Offset 0x0206 - PCIe Physical Slot Number per root port
+ Physical Slot Number per root port
+**/
+ UINT16 PegPhysicalSlotNumber[3];
+
+/** Offset 0x020C - PCIe DeEmphasis control per root port
0: -6dB, 1(Default): -3.5dB
0:Disable, 2:L1
**/
UINT8 PegDeEmphasis[3];
-/** Offset 0x0209 - PCIe Slot Power Limit value per root port
+/** Offset 0x020F - PCIe Slot Power Limit value per root port
Slot power limit value per root port
**/
UINT8 PegSlotPowerLimitValue[3];
-/** Offset 0x020C - PCIe Slot Power Limit scale per root port
+/** Offset 0x0212 - PCIe Slot Power Limit scale per root port
Slot power limit scale per root port
0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x
**/
UINT8 PegSlotPowerLimitScale[3];
-/** Offset 0x020F - PCIe Physical Slot Number per root port
- Physical Slot Number per root port
-**/
- UINT16 PegPhysicalSlotNumber[3];
-
/** Offset 0x0215 - Enable/Disable PavpEnable
Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
$EN_DIS
@@ -528,14 +528,18 @@ typedef struct {
**/
UINT8 X2ApicOptOut;
-/** Offset 0x021B - Base addresses for VT-d function MMIO access
+/** Offset 0x021B
+**/
+ UINT8 UnusedUpdSpace7[1];
+
+/** Offset 0x021C - Base addresses for VT-d function MMIO access
Base addresses for VT-d MMIO access per VT-d engine
**/
UINT32 VtdBaseAddress[2];
-/** Offset 0x0223
+/** Offset 0x0224
**/
- UINT8 UnusedUpdSpace7[20];
+ UINT8 UnusedUpdSpace8[19];
/** Offset 0x0237 - SaPostMemProductionRsvd
Reserved for SA Post-Mem Production
@@ -545,7 +549,7 @@ typedef struct {
/** Offset 0x0247
**/
- UINT8 UnusedUpdSpace8[7];
+ UINT8 UnusedUpdSpace9[7];
/** Offset 0x024E - Power State 3 enable/disable
PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
@@ -645,58 +649,62 @@ typedef struct {
/** Offset 0x027D
**/
- UINT8 UnusedUpdSpace9[8];
+ UINT8 UnusedUpdSpace10[9];
-/** Offset 0x0285 - Thermal Design Current current limit
+/** Offset 0x0286 - Thermal Design Current current limit
PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
**/
UINT16 TdcPowerLimit[5];
-/** Offset 0x028F
+/** Offset 0x0290
**/
- UINT8 UnusedUpdSpace10[10];
+ UINT8 UnusedUpdSpace11[8];
-/** Offset 0x0299 - AcLoadline
+/** Offset 0x0298 - AcLoadline
PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
**/
UINT16 AcLoadline[5];
-/** Offset 0x02A3 - DcLoadline
+/** Offset 0x02A2 - DcLoadline
PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
**/
UINT16 DcLoadline[5];
-/** Offset 0x02AD - Power State 1 Threshold current
+/** Offset 0x02AC - Power State 1 Threshold current
PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is
0-128A. Default Value = 20A.
**/
UINT16 Psi1Threshold[5];
-/** Offset 0x02B7 - Power State 2 Threshold current
+/** Offset 0x02B6 - Power State 2 Threshold current
PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is
0-128A. Default Value = 5A.
**/
UINT16 Psi2Threshold[5];
-/** Offset 0x02C1 - Power State 3 Threshold current
+/** Offset 0x02C0 - Power State 3 Threshold current
PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is
0-128A. Default Value = 1A.
**/
UINT16 Psi3Threshold[5];
-/** Offset 0x02CB - Icc Max limit
+/** Offset 0x02CA - Icc Max limit
PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
**/
UINT16 IccMax[5];
-/** Offset 0x02D5 - VR Voltage Limit
+/** Offset 0x02D4 - VR Voltage Limit
PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
**/
UINT16 VrVoltageLimit[5];
+/** Offset 0x02DE
+**/
+ UINT8 UnusedUpdSpace12;
+
/** Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain
Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
feature enabled. <b>0: False</b>; 1: True
@@ -713,7 +721,7 @@ typedef struct {
/** Offset 0x02E1
**/
- UINT8 UnusedUpdSpace11;
+ UINT8 UnusedUpdSpace13;
/** Offset 0x02E2 - Enable VR specific mailbox command
VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A
@@ -730,32 +738,30 @@ typedef struct {
**/
UINT8 SendVrMbxCmd1;
-/** Offset 0x02E4
-**/
- UINT8 UnusedUpdSpace12;
-
-/** Offset 0x02E5 - CpuS3ResumeMtrrData
+/** Offset 0x02E4 - CpuS3ResumeMtrrData
Pointer CPU S3 Resume MTRR Data
**/
UINT32 CpuS3ResumeMtrrData;
-/** Offset 0x02E9 - CpuS3ResumeMtrrDataSize
- Size of S3 resume MTRR data.
+/** Offset 0x02E8 - Cpu Configuration
+ Cpu Configuration data.
**/
- UINT16 CpuS3ResumeMtrrDataSize;
+ CPU_CONFIG_FSP_DATA CpuConfig;
-/** Offset 0x02EB
+/** Offset 0x02F0 - MicrocodePatchAddress
+ Pointer to microcode patch that is suitable for this processor.
+ 0:Disable, 1:Enable
**/
- UINT8 UnusedUpdSpace13[2];
+ UINT64 MicrocodePatchAddress;
-/** Offset 0x02ED - Cpu Configuration
+/** Offset 0x02F8 - CpuS3ResumeMtrrDataSize
Size of S3 resume MTRR data.
**/
- CPU_CONFIG_FSP_DATA CpuConfig;
+ UINT16 CpuS3ResumeMtrrDataSize;
-/** Offset 0x02F9
+/** Offset 0x02FA
**/
- UINT16 UnusedUpdSpace14;
+ UINT8 UnusedUpdSpace14;
/** Offset 0x02FB - Enable SkyCam PortA Termination override
Enable/disable PortA Termination override.
@@ -976,26 +982,26 @@ typedef struct {
**/
UINT8 PchHdaDspEndpointBluetooth;
-/** Offset 0x0340 - DSP I2S enablement
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchHdaDspEndpointI2s;
-
-/** Offset 0x0341 - Bitmask of supported DSP features
+/** Offset 0x0340 - Bitmask of supported DSP features
[BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6]
- BT Intel A2DP; [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0:
Intel WoV, 1: Windows Voice Activation.
**/
UINT32 PchHdaDspFeatureMask;
-/** Offset 0x0345 - Bitmask of supported DSP Pre/Post-Processing Modules
+/** Offset 0x0344 - Bitmask of supported DSP Pre/Post-Processing Modules
Deprecated: Specific pre/post-processing module bit position must be coherent with
the ACPI implementation: \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing
Module Support.
**/
UINT32 PchHdaDspPpModuleMask;
+/** Offset 0x0348 - DSP I2S enablement
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchHdaDspEndpointI2s;
+
/** Offset 0x0349 - Enable PCH Io Apic
Set to 1 if BDF value is valid.
$EN_DIS
@@ -1159,25 +1165,31 @@ typedef struct {
**/
UINT8 PchLockDownSpiEiss;
-/** Offset 0x0365 - PCH Sub system vendor ID
+/** Offset 0x0365 - PCH Compatibility Revision ID
+ This member describes whether or not the CRID feature of PCH should be enabled.
+ $EN_DIS
+**/
+ UINT8 PchCrid;
+
+/** Offset 0x0366 - PCH Sub system vendor ID
Default Subsystem Vendor ID of the PCH devices. Default is 0x8086.
**/
UINT16 PchSubSystemVendorId;
-/** Offset 0x0367 - PCH Sub system ID
+/** Offset 0x0368 - PCH Sub system ID
Default Subsystem ID of the PCH devices. Default is 0x7270.
**/
UINT16 PchSubSystemId;
-/** Offset 0x0369 - PCH Compatibility Revision ID
- This member describes whether or not the CRID feature of PCH should be enabled.
+/** Offset 0x036A - PCH Legacy IO Low Latency Enable
+ todo
$EN_DIS
**/
- UINT8 PchCrid;
+ UINT8 PchLegacyIoLowLatency;
-/** Offset 0x036A
+/** Offset 0x036B
**/
- UINT8 UnusedUpdSpace15[6];
+ UINT8 UnusedUpdSpace15[5];
/** Offset 0x0370 - Enable PCIE RP HotPlug
Indicate whether the root port is hot plug available.
@@ -1350,28 +1362,34 @@ typedef struct {
**/
UINT8 PcieComplianceTestMode;
-/** Offset 0x0636 - PCIE Rp Function Swap
+/** Offset 0x0636 - PCIE Rp Detect Timeout Ms
+ Will wait for link to exit Detect state for enabled ports before assuming there
+ is no device and potentially disabling the port.
+**/
+ UINT16 PcieDetectTimeoutMs;
+
+/** Offset 0x0638 - PCIE Rp Function Swap
Allows BIOS to use root port function number swapping when root port of function
0 is disabled.
$EN_DIS
**/
UINT8 PcieRpFunctionSwap;
-/** Offset 0x0637 - PCIE Rp Detect Timeout Ms
- Will wait for link to exit Detect state for enabled ports before assuming there
- is no device and potentially disabling the port.
-**/
- UINT16 PcieDetectTimeoutMs;
-
/** Offset 0x0639 - PCH Pm PME_B0_S5_DIS
When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
$EN_DIS
**/
UINT8 PchPmPmeB0S5Dis;
-/** Offset 0x063A
+/** Offset 0x063A - PCH Pm Slp S0 Voltage Margining Enable
+ Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state.
+ $EN_DIS
+**/
+ UINT8 PchPmSlpS0VmEnable;
+
+/** Offset 0x063B
**/
- UINT8 UnusedUpdSpace16[6];
+ UINT8 UnusedUpdSpace16[5];
/** Offset 0x0640 - PCH Pm Wol Enable Override
Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
@@ -1499,11 +1517,9 @@ typedef struct {
**/
UINT8 PchPmPwrCycDur;
-/** Offset 0x065B - PCH Pm Pcie Pll Ssc
- Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
- BIOS override.
+/** Offset 0x065B
**/
- UINT8 PchPmPciePllSsc;
+ UINT8 UnusedUpdSpace18;
/** Offset 0x065C - PCH Pm WOL_OVR_WK_STS
Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
@@ -1575,7 +1591,7 @@ typedef struct {
/** Offset 0x06B0 - PCH Sata Rst Raid Alternate Id
Enable RAID Alternate ID.
- $EN_DIS
+ 0:Client, 1:Alternate, 2:Server
**/
UINT8 SataRstRaidAlternateId;
@@ -1741,27 +1757,27 @@ typedef struct {
**/
UINT8 PchThermalDeviceEnable;
-/** Offset 0x06DC - Thermal Device SMI Enable
- This locks down SMI Enable on Alert Thermal Sensor Trip.
- $EN_DIS
-**/
- UINT8 PchTsmicLock;
-
-/** Offset 0x06DD - Thermal Throttling Custimized T0Level Value
+/** Offset 0x06DC - Thermal Throttling Custimized T0Level Value
Custimized T0Level value.
**/
UINT16 PchT0Level;
-/** Offset 0x06DF - Thermal Throttling Custimized T1Level Value
+/** Offset 0x06DE - Thermal Throttling Custimized T1Level Value
Custimized T1Level value.
**/
UINT16 PchT1Level;
-/** Offset 0x06E1 - Thermal Throttling Custimized T2Level Value
+/** Offset 0x06E0 - Thermal Throttling Custimized T2Level Value
Custimized T2Level value.
**/
UINT16 PchT2Level;
+/** Offset 0x06E2 - Thermal Device SMI Enable
+ This locks down SMI Enable on Alert Thermal Sensor Trip.
+ $EN_DIS
+**/
+ UINT8 PchTsmicLock;
+
/** Offset 0x06E3 - Enable The Thermal Throttle
Enable the thermal throttle function.
$EN_DIS
@@ -1946,7 +1962,7 @@ typedef struct {
/** Offset 0x0720
**/
- UINT32 UnusedUpdSpace18;
+ UINT8 UnusedUpdSpace19[4];
/** Offset 0x0724 - Pch PCIE device override table pointer
The PCIe device table is being used to override PCIe device ASPM settings. This
@@ -1964,130 +1980,144 @@ typedef struct {
**/
UINT8 EnableTcoTimer;
-/** Offset 0x0729 - BgpdtHash[4]
- BgpdtHash values
+/** Offset 0x0729 - EcCmdProvisionEav
+ Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
**/
- UINT64 BgpdtHash[4];
+ UINT8 EcCmdProvisionEav;
-/** Offset 0x0749 - BiosGuardAttr
- BiosGuardAttr default values
+/** Offset 0x072A - EcCmdLock
+ EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
**/
- UINT32 BiosGuardAttr;
+ UINT8 EcCmdLock;
-/** Offset 0x074D - BiosGuardModulePtr
- BiosGuardModulePtr default values
+/** Offset 0x072B
**/
- UINT64 BiosGuardModulePtr;
+ UINT8 UnusedUpdSpace20[5];
-/** Offset 0x0755 - SendEcCmd
+/** Offset 0x0730 - SendEcCmd
SendEcCmd function pointer. \n
@code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
**/
UINT64 SendEcCmd;
-/** Offset 0x075D - EcCmdProvisionEav
- Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
+/** Offset 0x0738 - BgpdtHash[4]
+ BgpdtHash values
**/
- UINT8 EcCmdProvisionEav;
+ UINT64 BgpdtHash[4];
-/** Offset 0x075E - EcCmdLock
- EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
+/** Offset 0x0758 - BiosGuardModulePtr
+ BiosGuardModulePtr default values
**/
- UINT8 EcCmdLock;
+ UINT64 BiosGuardModulePtr;
+
+/** Offset 0x0760 - BiosGuardAttr
+ BiosGuardAttr default values
+**/
+ UINT32 BiosGuardAttr;
-/** Offset 0x075F - SgxEpoch0
+/** Offset 0x0764 - SgxSinitNvsData
+ SgxSinitNvsData default values
+**/
+ UINT8 SgxSinitNvsData;
+
+/** Offset 0x0765
+**/
+ UINT8 UnusedUpdSpace21[3];
+
+/** Offset 0x0768 - SgxEpoch0
SgxEpoch0 default values
**/
UINT64 SgxEpoch0;
-/** Offset 0x0767 - SgxEpoch1
+/** Offset 0x0770 - SgxEpoch1
SgxEpoch1 default values
**/
UINT64 SgxEpoch1;
-/** Offset 0x076F - SgxSinitNvsData
- SgxSinitNvsData default values
+/** Offset 0x0778 - Enable/Disable ME Unconfig on RTC clear
+ Enable(Default): Enable ME Unconfig On Rtc Clear, Disable: Disable ME Unconfig On Rtc Clear
+ $EN_DIS
**/
- UINT8 SgxSinitNvsData;
+ UINT8 MeUnconfigOnRtcClear;
-/** Offset 0x0770
+/** Offset 0x0779
**/
- UINT8 ReservedFspsUpd[13];
+ UINT8 ReservedFspsUpd[7];
} FSP_S_CONFIG;
/** Fsp S Test Configuration
**/
typedef struct {
-/** Offset 0x077D
+/** Offset 0x0780
**/
UINT32 Signature;
-/** Offset 0x0781 - Enable/Disable Device 7
+/** Offset 0x0784 - Enable/Disable Device 7
Enable: Device 7 enabled, Disable (Default): Device 7 disabled
$EN_DIS
**/
UINT8 ChapDeviceEnable;
-/** Offset 0x0782 - Skip PAM regsiter lock
+/** Offset 0x0785 - Skip PAM regsiter lock
Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
PAM registers will be locked by RC
$EN_DIS
**/
UINT8 SkipPamLock;
-/** Offset 0x0783 - EDRAM Test Mode
+/** Offset 0x0786 - EDRAM Test Mode
Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
PAM registers will be locked by RC
0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
**/
UINT8 EdramTestMode;
-/** Offset 0x0784 - DMI Extended Sync Control
+/** Offset 0x0787 - DMI Extended Sync Control
Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended
Sync Control
$EN_DIS
**/
UINT8 DmiExtSync;
-/** Offset 0x0785 - DMI IOT Control
+/** Offset 0x0788 - DMI IOT Control
Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control
$EN_DIS
**/
UINT8 DmiIot;
-/** Offset 0x0786 - PEG Max Payload size per root port
+/** Offset 0x0789 - PEG Max Payload size per root port
0xFF(Default):Auto, 0x1: Force 128B, 0X2: Force 256B
0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
**/
UINT8 PegMaxPayload[3];
-/** Offset 0x0789 - Enable/Disable IGFX RenderStandby
+/** Offset 0x078C - Enable/Disable IGFX RenderStandby
Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
$EN_DIS
**/
UINT8 RenderStandby;
-/** Offset 0x078A - Enable/Disable IGFX PmSupport
+/** Offset 0x078D - Enable/Disable IGFX PmSupport
Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
$EN_DIS
**/
UINT8 PmSupport;
-/** Offset 0x078B - Enable/Disable CdynmaxClamp
+/** Offset 0x078E - Enable/Disable CdynmaxClamp
Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
$EN_DIS
**/
UINT8 CdynmaxClampEnable;
-/** Offset 0x078C - Disable VT-d
+/** Offset 0x078F - Disable VT-d
0=Enable/FALSE(VT-d disabled), 1=Disable/TRUE (VT-d enabled)
$EN_DIS
**/
UINT8 VtdDisable;
-/** Offset 0x078D - GT Frequency Limit
+/** Offset 0x0790 - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
@@ -2101,15 +2131,11 @@ typedef struct {
**/
UINT8 GtFreqMax;
-/** Offset 0x078E - SaPostMemTestRsvd
+/** Offset 0x0791 - SaPostMemTestRsvd
Reserved for SA Post-Mem Test
$EN_DIS
**/
- UINT8 SaPostMemTestRsvd[12];
-
-/** Offset 0x079A
-**/
- UINT16 UnusedUpdSpace19;
+ UINT8 SaPostMemTestRsvd[11];
/** Offset 0x079C - 1-Core Ratio Limit
1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
@@ -2145,7 +2171,7 @@ typedef struct {
/** Offset 0x07A0
**/
- UINT8 UnusedUpdSpace20;
+ UINT8 UnusedUpdSpace22;
/** Offset 0x07A1 - Enable or Disable HWP
Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
@@ -2323,7 +2349,7 @@ typedef struct {
/** Offset 0x07BC
**/
- UINT16 UnusedUpdSpace21;
+ UINT8 UnusedUpdSpace23[2];
/** Offset 0x07BE - Enable or Disable MLC Streamer Prefetcher
Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
@@ -2375,7 +2401,7 @@ typedef struct {
/** Offset 0x07C6
**/
- UINT16 UnusedUpdSpace22;
+ UINT8 UnusedUpdSpace24[2];
/** Offset 0x07C8 - Control on Processor Trace output scheme
Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
@@ -2390,17 +2416,20 @@ typedef struct {
UINT8 ProcTraceEnable;
/** Offset 0x07CA - Memory region allocation for Processor Trace
- Memory region allocation for Processor Trace, Valid Values are 0 - 4KB , 0x1 - 8KB
- , 0x2 - 16KB , 0x3 - 32KB , 0x4 - 64KB , 0x5 - 128KB , 0x6 - 256KB , 0x7 - 512KB
- , 0x8 - 1MB , 0x9 - 2MB , 0xA - 4MB , 0xB - 8MB , 0xC - 16MB , 0xD - 32MB , 0xE
- - 64MB , 0xF - 128MB , 0xFF: Disable
+ Memory region allocation for Processor Trace, Total Memory required is up to requested
+ value * 2 (for memory alignment) * 8 active threads, to enable Processor Trace,
+ PcdFspReservedMemoryLength must be increased by the total memory required, and
+ PlatformMemorySize policy must also be increased by the total memory required over
+ 32MB, Valid Values are 0 - 4KB , 0x1 - 8KB , 0x2 - 16KB , 0x3 - 32KB , 0x4 - 64KB
+ , 0x5 - 128KB , 0x6 - 256KB , 0x7 - 512KB , 0x8 - 1MB , 0x9 - 2MB , 0xA - 4MB ,
+ 0xB - 8MB , 0xC - 16MB , 0xD - 32MB , 0xE - 64MB , 0xF - 128MB , 0xFF: Disable
0x0:0xFF
**/
UINT8 ProcTraceMemSize;
/** Offset 0x07CB
**/
- UINT8 UnusedUpdSpace23;
+ UINT8 UnusedUpdSpace25;
/** Offset 0x07CC - Enable or Disable Voltage Optimization feature
Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b>
@@ -2588,160 +2617,160 @@ typedef struct {
**/
UINT8 ConfigTdpLevel;
-/** Offset 0x07E9 - Max P-State Ratio
+/** Offset 0x07E9 - Race To Halt
+ Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
+ in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
+ through MSR 1FC bit 20)Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 RaceToHalt;
+
+/** Offset 0x07EA - Max P-State Ratio
Max P-State Ratio , Valid Range 0 to 0x7F
0x0:0xFFFF
**/
UINT16 MaxRatio;
-/** Offset 0x07EB - Maximum P-state ratio to use in the custom P-state table
+/** Offset 0x07EC - Maximum P-state ratio to use in the custom P-state table
Maximum P-state ratio to use in the custom P-state table. NumOfCustomPStates has
valid range between 0 to 40. For no. of P-States supported(NumOfCustomPStates)
, StateRatio[NumOfCustomPStates] are configurable. Valid Range of value is 0 to 0x7F
**/
UINT16 StateRatio[40];
-/** Offset 0x083B - Platform Power Pmax
- PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
- Range 0-1024 Watts. Value of 800 = 100W
- 0x0:0xFFFF
-**/
- UINT16 PsysPmax;
-
-/** Offset 0x083D - Interrupt Response Time Limit of C-State LatencyContol0
+/** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol0
Interrupt Response Time Limit of C-State LatencyContol0. Range of value 0 to 0x3FF
0x0:0xFFFF
**/
UINT16 CstateLatencyControl0Irtl;
-/** Offset 0x083F - Interrupt Response Time Limit of C-State LatencyContol1
+/** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol1
Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
0x0:0xFFFF
**/
UINT16 CstateLatencyControl1Irtl;
-/** Offset 0x0841 - Interrupt Response Time Limit of C-State LatencyContol2
+/** Offset 0x0840 - Interrupt Response Time Limit of C-State LatencyContol2
Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF
0x0:0xFFFF
**/
UINT16 CstateLatencyControl2Irtl;
-/** Offset 0x0843 - Interrupt Response Time Limit of C-State LatencyContol3
+/** Offset 0x0842 - Interrupt Response Time Limit of C-State LatencyContol3
Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF
0x0:0xFFFF
**/
UINT16 CstateLatencyControl3Irtl;
-/** Offset 0x0845 - Interrupt Response Time Limit of C-State LatencyContol4
+/** Offset 0x0844 - Interrupt Response Time Limit of C-State LatencyContol4
Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF
0x0:0xFFFF
**/
UINT16 CstateLatencyControl4Irtl;
-/** Offset 0x0847 - Interrupt Response Time Limit of C-State LatencyContol5
+/** Offset 0x0846 - Interrupt Response Time Limit of C-State LatencyContol5
Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF
0x0:0xFFFF
**/
UINT16 CstateLatencyControl5Irtl;
-/** Offset 0x0849 - Package Long duration turbo mode power limit
+/** Offset 0x0848 - Package Long duration turbo mode power limit
Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
Valid Range 0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 PowerLimit1;
-/** Offset 0x084D - Package Short duration turbo mode power limit
+/** Offset 0x084C - Package Short duration turbo mode power limit
Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 PowerLimit2Power;
-/** Offset 0x0851 - Package PL3 power limit
+/** Offset 0x0850 - Package PL3 power limit
Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 PowerLimit3;
-/** Offset 0x0855 - Package PL4 power limit
+/** Offset 0x0854 - Package PL4 power limit
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 PowerLimit4;
-/** Offset 0x0859 - Tcc Offset Time Window for RATL
+/** Offset 0x0858 - Tcc Offset Time Window for RATL
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 TccOffsetTimeWindowForRatl;
-/** Offset 0x085D - Short term Power Limit value for custom cTDP level 1
+/** Offset 0x085C - Short term Power Limit value for custom cTDP level 1
Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 Custom1PowerLimit1;
-/** Offset 0x0861 - Long term Power Limit value for custom cTDP level 1
+/** Offset 0x0860 - Long term Power Limit value for custom cTDP level 1
Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 Custom1PowerLimit2;
-/** Offset 0x0865 - Short term Power Limit value for custom cTDP level 2
+/** Offset 0x0864 - Short term Power Limit value for custom cTDP level 2
Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 Custom2PowerLimit1;
-/** Offset 0x0869 - Long term Power Limit value for custom cTDP level 2
+/** Offset 0x0868 - Long term Power Limit value for custom cTDP level 2
Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 Custom2PowerLimit2;
-/** Offset 0x086D - Short term Power Limit value for custom cTDP level 3
+/** Offset 0x086C - Short term Power Limit value for custom cTDP level 3
Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 Custom3PowerLimit1;
-/** Offset 0x0871 - Long term Power Limit value for custom cTDP level 3
+/** Offset 0x0870 - Long term Power Limit value for custom cTDP level 3
Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 Custom3PowerLimit2;
-/** Offset 0x0875 - Platform PL1 power
+/** Offset 0x0874 - Platform PL1 power
Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 PsysPowerLimit1Power;
-/** Offset 0x0879 - Platform PL2 power
+/** Offset 0x0878 - Platform PL2 power
Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
0 to 4095875 in Step size of 125
0x0:0xFFFFFFFF
**/
UINT32 PsysPowerLimit2Power;
-/** Offset 0x087D - Race To Halt
- Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
- in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
- through MSR 1FC bit 20)Disable; <b>1: Enable</b>
- $EN_DIS
+/** Offset 0x087C - Platform Power Pmax
+ PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
+ Range 0-1024 Watts. Value of 800 = 100W
+ 0x0:0xFFFF
**/
- UINT8 RaceToHalt;
+ UINT16 PsysPmax;
/** Offset 0x087E - ReservedCpuPostMemTest
Reserved for CPU Post-Mem Test
@@ -2768,17 +2797,17 @@ typedef struct {
**/
UINT8 DisableD0I3SettingForHeci;
-/** Offset 0x088D - HD Audio Reset Wait Timer
- The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
-**/
- UINT16 PchHdaResetWaitTimer;
-
-/** Offset 0x088F - Enable LOCKDOWN SMI
+/** Offset 0x088D - Enable LOCKDOWN SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
$EN_DIS
**/
UINT8 PchLockDownGlobalSmi;
+/** Offset 0x088E - HD Audio Reset Wait Timer
+ The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
+**/
+ UINT16 PchHdaResetWaitTimer;
+
/** Offset 0x0890 - Enable LOCKDOWN BIOS Interface
Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
$EN_DIS
@@ -2911,19 +2940,19 @@ typedef struct {
**/
FSP_S_CONFIG FspsConfig;
-/** Offset 0x077D
+/** Offset 0x0780
**/
FSP_S_TEST_CONFIG FspsTestConfig;
/** Offset 0x0A40
**/
- UINT8 UnusedUpdSpace24[474];
+ UINT8 UnusedUpdSpace26[470];
-/** Offset 0x0C1A
+/** Offset 0x0C16
**/
UINT16 UpdTerminator;
} FSPS_UPD;
-#pragma pack(pop)
+#pragma pack()
#endif
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