[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Pass proper CPU flex ratio override

[Naresh Solanki (naresh.solanki@intel.com)]

Naresh Solanki (naresh.solanki at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17555

-gerrit

commit 03cb1c37c978be30784f6de898569042695f3d9d
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date:   Wed Nov 16 21:34:41 2016 +0530

    soc/intel/skylake: Pass proper CPU flex ratio override
    
    FSP expects proper CPU flex ratio to be supplied in UPD.
    
    Since flex ratio msr programming is already done in boot block, pass the
    same in UPD.
    
    Change-Id: I8cae5530ec97cedfbd71771f291db6f55a9fd5c2
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
 src/soc/intel/skylake/romstage/romstage_fsp20.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 8e08323..20a55fb 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -19,12 +19,14 @@
 #include <arch/symbols.h>
 #include <assert.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
 #include <cbmem.h>
 #include <chip.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <fsp/util.h>
 #include <fsp/memmap.h>
+#include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
@@ -94,6 +96,17 @@ asmlinkage void *car_stage_c_entry(void)
 	return postcar_commit_mtrrs(&pcf);
 }
 
+static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
+{
+	msr_t flex_ratio;
+	m_cfg->CpuRatioOverride = 1;
+	/* Set cpuratio to that we set in bootblock, This will ensure fspm know
+	 * what flex ration we intend to use.
+	 */
+	flex_ratio = rdmsr(MSR_FLEX_RATIO);
+	m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
+}
+
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
 {
 	const struct device *dev;
@@ -130,6 +143,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
 			mask |= (1<<i);
 	}
 	m_cfg->PcieRpEnableMask = mask;
+
+	cpu_flex_override(m_cfg);
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)