[coreboot-gerrit] New patch to review for coreboot: AGESA f14: Consolidate XIP cache
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Tue Nov 22 05:42:22 CET 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17563
-gerrit
commit a97f74d49c4b8c369f6e3ca053c48e2351ac7d18
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sun Nov 20 07:45:17 2016 +0200
AGESA f14: Consolidate XIP cache
Do this like fam15tn to reduce code duplication.
Change-Id: I064fd27b85be7fb0c9d6918a84fc6f9b17065534
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/amd/agesa/family14/fixme.c | 6 ++++++
src/mainboard/amd/inagua/romstage.c | 6 ------
src/mainboard/amd/persimmon/romstage.c | 7 -------
src/mainboard/amd/south_station/romstage.c | 7 -------
src/mainboard/amd/union_station/romstage.c | 7 -------
src/mainboard/asrock/e350m1/romstage.c | 7 -------
src/mainboard/elmex/pcm205400/romstage.c | 7 -------
src/mainboard/gizmosphere/gizmo/romstage.c | 11 -----------
src/mainboard/jetway/nf81-t56n-lf/romstage.c | 7 -------
src/mainboard/lippert/frontrunner-af/romstage.c | 7 -------
src/mainboard/lippert/toucan-af/romstage.c | 7 -------
src/mainboard/pcengines/apu1/romstage.c | 7 -------
12 files changed, 6 insertions(+), 80 deletions(-)
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index d1bd0a1..bfc56d4 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -92,6 +92,12 @@ void amd_initmmio(void)
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set ROM cache onto WP to decrease post time */
+ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
+ LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
+ LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
}
void amd_initenv(void)
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 385328c..151ce31 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -40,12 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /* all cores: allow caching of flash chip code and data
- * (there are no cache-as-ram reliability concerns with family 14h)
- */
- __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
- __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
-
/* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
*/
__writemsr (0xc0010062, 0);
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 0aad4f5..d553c1b 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -46,13 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /*
- * All cores: allow caching of flash chip code and data
- * (there are no cache-as-ram reliability concerns with family 14h)
- */
- __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
- __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
-
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index d37ea0a..5ef95a0 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -41,13 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /*
- * All cores: allow caching of flash chip code and data
- * (there are no cache-as-ram reliability concerns with family 14h)
- */
- __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
- __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
-
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index eddcf29..cdc5640 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -39,13 +39,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /*
- * All cores: allow caching of flash chip code and data
- * (there are no cache-as-ram reliability concerns with family 14h)
- */
- __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
- __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
-
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 50f3f6b..6d2cad2 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -43,13 +43,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /*
- * All cores: allow caching of flash chip code and data
- * (there are no cache-as-ram reliability concerns with family 14h)
- */
- __writemsr(0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
- __writemsr(0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
-
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr(0xc0010062, 0);
diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c
index 0aad4f5..d553c1b 100644
--- a/src/mainboard/elmex/pcm205400/romstage.c
+++ b/src/mainboard/elmex/pcm205400/romstage.c
@@ -46,13 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /*
- * All cores: allow caching of flash chip code and data
- * (there are no cache-as-ram reliability concerns with family 14h)
- */
- __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
- __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
-
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 972f5d0..e6276ff 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -47,17 +47,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
msr_t msr;
- /*
- * All cores: allow caching of flash chip code and data
- * (there are no cache-as-ram reliability concerns with family 14h)
- */
- msr.lo = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) & 0xFFFFFFFF;
- msr.hi = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) >> 32;
- wrmsr (MSR_MTRR_VARIABLE_BASE6, msr);
-
- msr.lo = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) & 0xFFFFFFFF;
- msr.hi = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) >> 32;
- wrmsr (MSR_MTRR_VARIABLE_MASK6, msr);
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
msr.lo = 0;
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 3deb9c3..ea2e11f 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -62,13 +62,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /*
- * All cores: allow caching of flash chip code and data
- * (there are no cache-as-ram reliability concerns with family 14h)
- */
- __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
- __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
-
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index cdfb31a..0beda77 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -45,13 +45,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /*
- * All cores: allow caching of flash chip code and data
- * (there are no cache-as-ram reliability concerns with family 14h)
- */
- __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
- __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
-
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 70cd622..44a27ca 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -46,13 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /*
- * All cores: allow caching of flash chip code and data
- * (there are no cache-as-ram reliability concerns with family 14h)
- */
- __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
- __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
-
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 13efcad..cf4f3fa 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -51,13 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /*
- * All cores: allow caching of flash chip code and data
- * (there are no cache-as-ram reliability concerns with family 14h)
- */
- __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
- __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
-
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
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