[coreboot-gerrit] Patch merged into coreboot/master: fsp2_0: implement stage cache for silicon init

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit c6ec8dd1cb2303f7f7a71f0f494a6fc30b93dff4
Author: Brandon Breitenstein <brandon.breitenstein at intel.com>
Date:   Thu Nov 17 12:23:04 2016 -0800

    fsp2_0: implement stage cache for silicon init
    
    Stage cache will save ~20ms on S3 resume for apollolake platforms.
    Implementing the cache in ramstage to save silicon init and reload
    it on resume. This patch adds passing S3 status to silicon init in
    order to verify that the wake is from S3 and not for some other
    reason. This patch also includes changes needed for quark and
    skylake platforms that require fsp 2.0.
    
    BUG=chrome-os-partner:56941
    BRANCH=none
    TEST=built for reef and tested boot and S3 resume path saving 20ms
    
    Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6
    Signed-off-by: Brandon Breitenstein <brandon.breitenstein at intel.com>
    Reviewed-on: https://review.coreboot.org/17460
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/17460 for details.

-gerrit