[coreboot-gerrit] New patch to review for coreboot: AGESA binaryPI: Fix cache-as-ram for x86_64

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17551

-gerrit

commit 1e5e583abe8a412b601ff48b7e66e2a9ba7d2f92
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Nov 21 11:26:48 2016 +0200

    AGESA binaryPI: Fix cache-as-ram for x86_64
    
    AMD_ENABLE_STACK was not called on x86_64 path for AGESA, while
    it was for binaryPI.
    
    Comments on BIST and cpu_init_detected where reversed.
    
    Change-Id: I0ddfaf51feb386a56d488c29d60171b05ff6fbc4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/amd/agesa/cache_as_ram.inc | 7 ++++---
 src/cpu/amd/pi/cache_as_ram.inc    | 6 ++++--
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index 293e9a5..24db600 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -61,6 +61,8 @@ cache_as_ram_setup:
 
   post_code(0xa1)
 
+  AMD_ENABLE_STACK
+
 #ifdef __x86_64__
   /* switch to 64 bit long mode */
   mov     %esi, %ecx
@@ -103,10 +105,10 @@ cache_as_ram_setup:
   # use call far to switch to 64-bit code segment
   ljmp $0x18, $1f
 1:
-  /* Pass the BIST result */
+  /* Pass the cpu_init_detected */
   cvtsd2si        %xmm1, %esi
 
-  /* Pass the cpu_init_detected */
+  /* Pass the BIST result */
   cvtsd2si        %xmm0, %edi
 
   /* align the stack */
@@ -117,7 +119,6 @@ cache_as_ram_setup:
   .code32
 
 #else
-  AMD_ENABLE_STACK
 
   /* Restore the BIST result */
   cvtsd2si  %xmm0, %edx
diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc
index 40ec1b2..24db600 100644
--- a/src/cpu/amd/pi/cache_as_ram.inc
+++ b/src/cpu/amd/pi/cache_as_ram.inc
@@ -62,6 +62,7 @@ cache_as_ram_setup:
   post_code(0xa1)
 
   AMD_ENABLE_STACK
+
 #ifdef __x86_64__
   /* switch to 64 bit long mode */
   mov     %esi, %ecx
@@ -104,10 +105,10 @@ cache_as_ram_setup:
   # use call far to switch to 64-bit code segment
   ljmp $0x18, $1f
 1:
-  /* Pass the BIST result */
+  /* Pass the cpu_init_detected */
   cvtsd2si        %xmm1, %esi
 
-  /* Pass the cpu_init_detected */
+  /* Pass the BIST result */
   cvtsd2si        %xmm0, %edi
 
   /* align the stack */
@@ -118,6 +119,7 @@ cache_as_ram_setup:
   .code32
 
 #else
+
   /* Restore the BIST result */
   cvtsd2si  %xmm0, %edx