[coreboot-gerrit] Patch merged into coreboot/master: intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit c13d65c29b6219d4b765f40e661548eb389524b5
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Nov 18 19:03:29 2016 +0200

    intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT
    
    Compiled romstage is over 64kiB and exceeded XIP_ROM_SIZE,
    so it was not entirely set WRPROT cacheable.
    
    Reduces first boot raminit (including training) time by 400ms.
    
    Change-Id: I5c4cbf581fc845150f207087c1527338ca364f60
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
    Reviewed-on: https://review.coreboot.org/17488
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Patrick Rudolph <siro at das-labor.org>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/17488 for details.

-gerrit