[coreboot-gerrit] Patch set updated for coreboot: intel PCI ops: Remove explicit PCI MMCONF access
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sun Nov 20 21:17:10 CET 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17529
-gerrit
commit b41540f3d74561d5bd34c0a6ff6ddcadb10afdd0
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Fri Jul 26 08:53:59 2013 +0300
intel PCI ops: Remove explicit PCI MMCONF access
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.
All these platforms now have MMCONF_SUPPORT_DEFAULT.
Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 2 +-
src/northbridge/intel/nehalem/raminit.c | 146 ++++++++++++-------------
src/northbridge/intel/nehalem/smi.c | 2 +-
src/northbridge/intel/sandybridge/raminit.c | 58 +++++-----
src/soc/intel/sch/smihandler.c | 6 +-
src/southbridge/intel/bd82x6x/early_me.c | 4 +-
src/southbridge/intel/bd82x6x/early_pch.c | 4 +-
src/southbridge/intel/bd82x6x/early_usb.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/finalize.c | 4 +-
src/southbridge/intel/fsp_bd82x6x/me.c | 10 +-
src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 8 +-
src/southbridge/intel/fsp_bd82x6x/smihandler.c | 12 +-
src/southbridge/intel/fsp_i89xx/finalize.c | 4 +-
src/southbridge/intel/fsp_i89xx/me.c | 10 +-
src/southbridge/intel/fsp_i89xx/me_8.x.c | 8 +-
src/southbridge/intel/fsp_i89xx/smihandler.c | 12 +-
16 files changed, 146 insertions(+), 146 deletions(-)
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index 06fee7e..49b3a89 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -95,7 +95,7 @@ void rcba_config(void)
RCBA32(0x35a0) = 0xc0300c03;
RCBA32(0x35a4) = 0x00241803;
- pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
+ pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
outw (0x0000, DEFAULT_PMBASE | 0x003c);
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 0d1696d..891ca0c 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -1446,9 +1446,9 @@ static void program_board_delay(struct raminfo *info)
write_mchbar16(0x612, read_mchbar16(0x612) | 0x100);
write_mchbar16(0x214, read_mchbar16(0x214) | 0x3E00);
for (i = 0; i < 8; i++) {
- pcie_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0x80 + 4 * i,
+ pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0x80 + 4 * i,
(info->total_memory_mb - 64) | !i | 2);
- pcie_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0xc0 + 4 * i, 0);
+ pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0xc0 + 4 * i, 0);
}
}
@@ -1492,7 +1492,7 @@ static void program_total_memory_map(struct raminfo *info)
#if REAL
if (info->uma_enabled) {
- u16 t = pcie_read_config16(NORTHBRIDGE, D0F0_GGC);
+ u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC);
gav(t);
const int uma_sizes_gtt[16] =
{ 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
@@ -1528,7 +1528,7 @@ static void program_total_memory_map(struct raminfo *info)
{
u32 t;
- gav(t = pcie_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68));
+ gav(t = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68));
if (t & 0x800)
quickpath_reserved =
(1 << find_lowest_bit_set32(t >> 20));
@@ -1538,7 +1538,7 @@ static void program_total_memory_map(struct raminfo *info)
#if !REAL
if (info->uma_enabled) {
- u16 t = pcie_read_config16(NORTHBRIDGE, D0F0_GGC);
+ u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC);
gav(t);
const int uma_sizes_gtt[16] =
{ 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
@@ -1560,29 +1560,29 @@ static void program_total_memory_map(struct raminfo *info)
tseg_base -= quickpath_reserved;
tseg_base = ALIGN_DOWN(tseg_base, 8);
- pcie_write_config16(NORTHBRIDGE, D0F0_TOLUD, TOLUD << 4);
- pcie_write_config16(NORTHBRIDGE, D0F0_TOM, TOM >> 6);
+ pci_write_config16(NORTHBRIDGE, D0F0_TOLUD, TOLUD << 4);
+ pci_write_config16(NORTHBRIDGE, D0F0_TOM, TOM >> 6);
if (memory_remap) {
- pcie_write_config16(NORTHBRIDGE, D0F0_REMAPBASE, REMAPbase >> 6);
- pcie_write_config16(NORTHBRIDGE, D0F0_REMAPLIMIT, (TOUUD - 64) >> 6);
+ pci_write_config16(NORTHBRIDGE, D0F0_REMAPBASE, REMAPbase >> 6);
+ pci_write_config16(NORTHBRIDGE, D0F0_REMAPLIMIT, (TOUUD - 64) >> 6);
}
- pcie_write_config16(NORTHBRIDGE, D0F0_TOUUD, TOUUD);
+ pci_write_config16(NORTHBRIDGE, D0F0_TOUUD, TOUUD);
if (info->uma_enabled) {
- pcie_write_config32(NORTHBRIDGE, D0F0_IGD_BASE, uma_base_igd << 20);
- pcie_write_config32(NORTHBRIDGE, D0F0_GTT_BASE, uma_base_gtt << 20);
+ pci_write_config32(NORTHBRIDGE, D0F0_IGD_BASE, uma_base_igd << 20);
+ pci_write_config32(NORTHBRIDGE, D0F0_GTT_BASE, uma_base_gtt << 20);
}
- pcie_write_config32(NORTHBRIDGE, TSEG, tseg_base << 20);
+ pci_write_config32(NORTHBRIDGE, TSEG, tseg_base << 20);
current_limit = 0;
memory_map[0] = ALIGN_DOWN(uma_base_gtt, 64) | 1;
memory_map[1] = 4096;
for (i = 0; i < ARRAY_SIZE(memory_map); i++) {
current_limit = max(current_limit, memory_map[i] & ~1);
- pcie_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80,
+ pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80,
(memory_map[i] & 1) | ALIGN_DOWN(current_limit -
1, 64) | 2);
- pcie_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0xc0, 0);
+ pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0xc0, 0);
}
}
@@ -1597,7 +1597,7 @@ static void collect_system_info(struct raminfo *info)
if (!info->heci_bar)
gav(info->heci_bar =
- pcie_read_config32(HECIDEV, HECIBAR) & 0xFFFFFFF8);
+ pci_read_config32(HECIDEV, HECIBAR) & 0xFFFFFFF8);
if (!info->memory_reserved_for_heci_mb) {
/* Wait for ME to be ready */
intel_early_me_init();
@@ -1606,15 +1606,15 @@ static void collect_system_info(struct raminfo *info)
for (i = 0; i < 3; i++)
gav(capid0[i] =
- pcie_read_config32(NORTHBRIDGE, D0F0_CAPID0 | (i << 2)));
- gav(info->revision = pcie_read_config8(NORTHBRIDGE, PCI_REVISION_ID));
+ pci_read_config32(NORTHBRIDGE, D0F0_CAPID0 | (i << 2)));
+ gav(info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID));
info->max_supported_clock_speed_index = (~capid0[1] & 7);
if ((capid0[1] >> 11) & 1)
info->uma_enabled = 0;
else
gav(info->uma_enabled =
- pcie_read_config8(NORTHBRIDGE, D0F0_DEVEN) & 8);
+ pci_read_config8(NORTHBRIDGE, D0F0_DEVEN) & 8);
/* Unrecognised: [0000:fffd3d2d] 37f81.37f82 ! CPUID: eax: 00000001; ecx: 00000e00 => 00020655.00010800.029ae3ff.bfebfbff */
info->silicon_revision = 0;
@@ -1641,7 +1641,7 @@ static void collect_system_info(struct raminfo *info)
info->silicon_revision = 2;
break;
}
- switch (pcie_read_config16(NORTHBRIDGE, PCI_DEVICE_ID)) {
+ switch (pci_read_config16(NORTHBRIDGE, PCI_DEVICE_ID)) {
case 0x40:
info->silicon_revision = 0;
break;
@@ -1936,20 +1936,20 @@ static void setup_heci_uma(struct raminfo *info)
{
u32 reg44;
- reg44 = pcie_read_config32(HECIDEV, 0x44); // = 0x80010020
+ reg44 = pci_read_config32(HECIDEV, 0x44); // = 0x80010020
info->memory_reserved_for_heci_mb = 0;
info->heci_uma_addr = 0;
- if (!((reg44 & 0x10000) && !(pcie_read_config32(HECIDEV, 0x40) & 0x20)))
+ if (!((reg44 & 0x10000) && !(pci_read_config32(HECIDEV, 0x40) & 0x20)))
return;
- info->heci_bar = pcie_read_config32(HECIDEV, 0x10) & 0xFFFFFFF0;
+ info->heci_bar = pci_read_config32(HECIDEV, 0x10) & 0xFFFFFFF0;
info->memory_reserved_for_heci_mb = reg44 & 0x3f;
info->heci_uma_addr =
((u64)
- ((((u64) pcie_read_config16(NORTHBRIDGE, D0F0_TOM)) << 6) -
+ ((((u64) pci_read_config16(NORTHBRIDGE, D0F0_TOM)) << 6) -
info->memory_reserved_for_heci_mb)) << 20;
- pcie_read_config32(NORTHBRIDGE, DMIBAR);
+ pci_read_config32(NORTHBRIDGE, DMIBAR);
if (info->memory_reserved_for_heci_mb) {
write32(DEFAULT_DMIBAR + 0x14,
read32(DEFAULT_DMIBAR + 0x14) & ~0x80);
@@ -1978,8 +1978,8 @@ static void setup_heci_uma(struct raminfo *info)
send_heci_uma_message(info);
- pcie_write_config32(HECIDEV, 0x10, 0x0);
- pcie_write_config8(HECIDEV, 0x4, 0x0);
+ pci_write_config32(HECIDEV, 0x10, 0x0);
+ pci_write_config8(HECIDEV, 0x4, 0x0);
}
@@ -2094,7 +2094,7 @@ static void flush_cache(u32 start, u32 size)
static void clear_errors(void)
{
- pcie_write_config8(NORTHBRIDGE, 0xc0, 0x01);
+ pci_write_config8(NORTHBRIDGE, 0xc0, 0x01);
}
static void write_testing(struct raminfo *info, int totalrank, int flip)
@@ -2989,7 +2989,7 @@ static int try_cached_training(struct raminfo *info)
write_mchbar8(0x243, saved_243[0] | 2);
write_mchbar8(0x643, saved_243[1] | 2);
set_ecc(0);
- pcie_write_config16(NORTHBRIDGE, 0xc8, 3);
+ pci_write_config16(NORTHBRIDGE, 0xc8, 3);
if (read_1d0(0x10b, 6) & 1)
set_10b(info, 0);
for (tm = 0; tm < 2; tm++) {
@@ -3155,7 +3155,7 @@ static void do_ram_training(struct raminfo *info)
write_testing_type2(info, totalrank, 2, i, 0);
write_testing_type2(info, totalrank, 3, i, 1);
}
- pcie_write_config8(NORTHBRIDGE, 0xc0, 0x01);
+ pci_write_config8(NORTHBRIDGE, 0xc0, 0x01);
totalrank++;
}
@@ -3838,20 +3838,20 @@ void chipset_init(const int s3resume)
ggc = 0xb00 | ((gfxsize + 5) << 4);
- pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc | 2);
+ pci_write_config16(NORTHBRIDGE, D0F0_GGC, ggc | 2);
u16 deven;
- deven = pcie_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3
+ deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3
if (deven & 8) {
write_mchbar8(0x2c30, 0x20);
- pcie_read_config8(NORTHBRIDGE, 0x8); // = 0x18
+ pci_read_config8(NORTHBRIDGE, 0x8); // = 0x18
write_mchbar16(0x2c30, read_mchbar16(0x2c30) | 0x200);
write_mchbar16(0x2c32, 0x434);
read_mchbar32(0x2c44);
write_mchbar32(0x2c44, 0x1053687);
- pcie_read_config8(GMA, 0x62); // = 0x2
- pcie_write_config8(GMA, 0x62, 0x2);
+ pci_read_config8(GMA, 0x62); // = 0x2
+ pci_write_config8(GMA, 0x62, 0x2);
read8(DEFAULT_RCBA + 0x2318);
write8(DEFAULT_RCBA + 0x2318, 0x47);
read8(DEFAULT_RCBA + 0x2320);
@@ -3861,7 +3861,7 @@ void chipset_init(const int s3resume)
read_mchbar32(0x30);
write_mchbar32(0x30, 0x40);
- pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc);
+ pci_write_config16(NORTHBRIDGE, D0F0_GGC, ggc);
gav(read32(DEFAULT_RCBA + 0x3428));
write32(DEFAULT_RCBA + 0x3428, 0x1d);
}
@@ -3876,7 +3876,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
int cbmem_wasnot_inited;
x2ca8 = read_mchbar8(0x2ca8);
- deven = pcie_read_config16(NORTHBRIDGE, D0F0_DEVEN);
+ deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN);
memset(&info, 0x5a, sizeof(info));
@@ -3904,7 +3904,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
timestamp_add_now(101);
if (!s3resume || REAL) {
- pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80
+ pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80
collect_system_info(&info);
@@ -4009,7 +4009,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
gav(0x55);
- gav(pcie_read_config32(NORTHBRIDGE, D0F0_CAPID0 + 4));
+ gav(pci_read_config32(NORTHBRIDGE, D0F0_CAPID0 + 4));
}
/* after SPD */
@@ -4024,11 +4024,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
calculate_timings(&info);
#if !REAL
- pcie_write_config8(NORTHBRIDGE, 0xdf, 0x82);
+ pci_write_config8(NORTHBRIDGE, 0xdf, 0x82);
#endif
if (!s3resume) {
- u8 reg8 = pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2);
+ u8 reg8 = pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2);
if (x2ca8 == 0 && (reg8 & 0x80)) {
/* Don't enable S4-assertion stretch. Makes trouble on roda/rk9.
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
@@ -4053,8 +4053,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
#endif
if (!s3resume && x2ca8 == 0)
- pcie_write_config8(SOUTHBRIDGE, GEN_PMCON_2,
- pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2) | 0x80);
+ pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2,
+ pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) | 0x80);
compute_derived_timings(&info);
@@ -4068,8 +4068,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar32(0x1890, read_mchbar32(0x1890) | 0x2000000); /* OK */
write_mchbar32(0x18b4, read_mchbar32(0x18b4) | 0x8000);
- gav(pcie_read_config32(PCI_DEV(0xff, 2, 1), 0x50)); // !!!!
- pcie_write_config8(PCI_DEV(0xff, 2, 1), 0x54, 0x12);
+ gav(pci_read_config32(PCI_DEV(0xff, 2, 1), 0x50)); // !!!!
+ pci_write_config8(PCI_DEV(0xff, 2, 1), 0x54, 0x12);
gav(read_mchbar16(0x2c10)); // !!!!
write_mchbar16(0x2c10, 0x412);
@@ -4080,8 +4080,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar32(0x1804,
(read_mchbar32(0x1804) & 0xfffffffc) | 0x8400080);
- pcie_read_config32(PCI_DEV(0xff, 2, 1), 0x6c); // !!!!
- pcie_write_config32(PCI_DEV(0xff, 2, 1), 0x6c, 0x40a0a0);
+ pci_read_config32(PCI_DEV(0xff, 2, 1), 0x6c); // !!!!
+ pci_write_config32(PCI_DEV(0xff, 2, 1), 0x6c, 0x40a0a0);
gav(read_mchbar32(0x1c04)); // !!!!
gav(read_mchbar32(0x1804)); // !!!!
@@ -4091,16 +4091,16 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar32(0x18d8, 0x120000);
write_mchbar32(0x18dc, 0x30a484a);
- pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x0);
- pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x9444a);
+ pci_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x0);
+ pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x9444a);
write_mchbar32(0x18d8, 0x40000);
write_mchbar32(0x18dc, 0xb000000);
- pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x60000);
- pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x0);
+ pci_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x60000);
+ pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x0);
write_mchbar32(0x18d8, 0x180000);
write_mchbar32(0x18dc, 0xc0000142);
- pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x20000);
- pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x142);
+ pci_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x20000);
+ pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x142);
write_mchbar32(0x18d8, 0x1e0000);
gav(read_mchbar32(0x18dc)); // !!!!
@@ -4112,7 +4112,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
}
write_mchbar32(0x188c, 0x20bc09);
- pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xd0, 0x40b0c09);
+ pci_write_config32(PCI_DEV(0xff, 2, 1), 0xd0, 0x40b0c09);
write_mchbar32(0x1a10, 0x4200010e);
write_mchbar32(0x18b8, read_mchbar32(0x18b8) | 0x200);
gav(read_mchbar32(0x1918)); // !!!!
@@ -4122,8 +4122,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar32(0x18b8, 0xe00);
gav(read_mchbar32(0x182c)); // !!!!
write_mchbar32(0x182c, 0x10202);
- gav(pcie_read_config32(PCI_DEV(0xff, 2, 1), 0x94)); // !!!!
- pcie_write_config32(PCI_DEV(0xff, 2, 1), 0x94, 0x10202);
+ gav(pci_read_config32(PCI_DEV(0xff, 2, 1), 0x94)); // !!!!
+ pci_write_config32(PCI_DEV(0xff, 2, 1), 0x94, 0x10202);
write_mchbar32(0x1a1c, read_mchbar32(0x1a1c) & 0x8fffffff);
write_mchbar32(0x1a70, read_mchbar32(0x1a70) | 0x100000);
@@ -4137,13 +4137,13 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) | 1); // guess
}
- pcie_read_config32(PCI_DEV(0xff, 2, 0), 0x048); // !!!!
- pcie_write_config32(PCI_DEV(0xff, 2, 0), 0x048, 0x140000);
- pcie_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!!
- pcie_write_config32(PCI_DEV(0xff, 2, 0), 0x058, 0x64555);
- pcie_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!!
- pcie_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!!
- pcie_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180);
+ pci_read_config32(PCI_DEV(0xff, 2, 0), 0x048); // !!!!
+ pci_write_config32(PCI_DEV(0xff, 2, 0), 0x048, 0x140000);
+ pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!!
+ pci_write_config32(PCI_DEV(0xff, 2, 0), 0x058, 0x64555);
+ pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!!
+ pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!!
+ pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180);
gav(read_mchbar32(0x1af0)); // !!!!
gav(read_mchbar32(0x1af0)); // !!!!
write_mchbar32(0x1af0, 0x1f020003);
@@ -4198,9 +4198,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar32(0xff8, 0x1800 | read_mchbar32(0xff8));
read_mchbar32(0x2cb0);
write_mchbar32(0x2cb0, 0x00);
- pcie_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
- pcie_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
- pcie_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e);
+ pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
+ pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
+ pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e);
read_mchbar8(0x1150);
read_mchbar8(0x1151);
@@ -4418,7 +4418,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar8(0x2ca8, read_mchbar8(0x2ca8));
read_mchbar32(0x2c80); // !!!!
write_mchbar32(0x2c80, 0x53688);
- pcie_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220);
+ pci_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220);
read_mchbar16(0x2c20); // !!!!
read_mchbar16(0x2c10); // !!!!
read_mchbar16(0x2c00); // !!!!
@@ -4743,7 +4743,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
}
/* was == 1 but is common */
- pcie_write_config16(NORTHBRIDGE, 0xc8, 3);
+ pci_write_config16(NORTHBRIDGE, 0xc8, 3);
write_26c(0, 0x820);
write_26c(1, 0x820);
write_mchbar32(0x130, read_mchbar32(0x130) | 2);
@@ -4876,12 +4876,12 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar32(0x290 + (channel << 10), 0x282091c | ((info.max_slots_used_in_channel - 1) << 0x16)); // OK
}
u32 reg1c;
- pcie_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
+ pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
reg1c = read32p(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
- pcie_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
+ pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
write32p(DEFAULT_EPBAR | 0x01c, reg1c); // OK
read_mchbar8(0xe08); // = 0x0
- pcie_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
+ pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
write_mchbar8(0x1210, read_mchbar8(0x1210) | 2); // OK
write_mchbar32(0x1200, 0x8800440); // OK
write_mchbar32(0x1204, 0x53ff0453); // OK
@@ -4963,8 +4963,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar16(0x1190, read_mchbar16(0x1190) & ~0x4000); // OK
}
- pcie_write_config8(SOUTHBRIDGE, GEN_PMCON_2,
- pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80);
+ pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2,
+ pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80);
udelay(10000);
write_mchbar16(0x2ca8, 0x8);
diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c
index faafdee..4a1a556 100644
--- a/src/northbridge/intel/nehalem/smi.c
+++ b/src/northbridge/intel/nehalem/smi.c
@@ -10,5 +10,5 @@
void northbridge_write_smram(u8 smram)
{
- pcie_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram);
+ pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram);
}
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 0842d4b..da7f34d 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -1156,98 +1156,98 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size)
printk(BIOS_DEBUG, "Update PCI-E configuration space:\n");
// TOM (top of memory)
- reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa0);
+ reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xa0);
val = tom & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa0, reg);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0xa0, reg);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0xa0, reg);
- reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa4);
+ reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xa4);
val = tom & 0xfffff000;
reg = (reg & ~0x000fffff) | (val >> 12);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa4, reg);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0xa4, reg);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, reg);
// TOLUD (top of low used dram)
- reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xbc);
+ reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xbc);
val = toludbase & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xbc, reg);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0xbc, reg);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0xbc, reg);
// TOUUD LSB (top of upper usable dram)
- reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa8);
+ reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xa8);
val = touudbase & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa8, reg);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0xa8, reg);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, reg);
// TOUUD MSB
- reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xac);
+ reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xac);
val = touudbase & 0xfffff000;
reg = (reg & ~0x000fffff) | (val >> 12);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xac, reg);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0xac, reg);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0xac, reg);
if (reclaim) {
// REMAP BASE
- pcie_write_config32(PCI_DEV(0, 0, 0), 0x90, remapbase << 20);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0x94, remapbase >> 12);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0x90, remapbase << 20);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0x94, remapbase >> 12);
// REMAP LIMIT
- pcie_write_config32(PCI_DEV(0, 0, 0), 0x98, remaplimit << 20);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0x9c, remaplimit >> 12);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0x98, remaplimit << 20);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0x9c, remaplimit >> 12);
}
// TSEG
- reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb8);
+ reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xb8);
val = tsegbase & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb8, reg);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0xb8, reg);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0xb8, reg);
// GFX stolen memory
- reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb0);
+ reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xb0);
val = gfxstolenbase & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb0, reg);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0xb0, reg);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0xb0, reg);
// GTT stolen memory
- reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb4);
+ reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xb4);
val = gttbase & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb4, reg);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0xb4, reg);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0xb4, reg);
if (me_uma_size) {
- reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x7c);
+ reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x7c);
val = (0x80000 - me_uma_size) & 0xfffff000;
reg = (reg & ~0x000fffff) | (val >> 12);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x7c, reg);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0x7c, reg);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0x7c, reg);
// ME base
- reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x70);
+ reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x70);
val = mestolenbase & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x70, reg);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0x70, reg);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0x70, reg);
- reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x74);
+ reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x74);
val = mestolenbase & 0xfffff000;
reg = (reg & ~0x000fffff) | (val >> 12);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x74, reg);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0x74, reg);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0x74, reg);
// ME mask
- reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x78);
+ reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x78);
val = (0x80000 - me_uma_size) & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20);
reg = (reg & ~0x400) | (1 << 10); // set lockbit on ME mem
reg = (reg & ~0x800) | (1 << 11); // set ME memory enable
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x78, reg);
- pcie_write_config32(PCI_DEV(0, 0, 0), 0x78, reg);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0x78, reg);
}
}
@@ -4208,7 +4208,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck,
wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 });
reg_5d10 = read32(DEFAULT_MCHBAR + 0x5d10); // !!! = 0x00000000
- if ((pcie_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */
+ if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */
&& reg_5d10 && !s3resume) {
write32(DEFAULT_MCHBAR + 0x5d10, 0);
/* Need reset. */
diff --git a/src/soc/intel/sch/smihandler.c b/src/soc/intel/sch/smihandler.c
index 57eb35c..6982f58 100644
--- a/src/soc/intel/sch/smihandler.c
+++ b/src/soc/intel/sch/smihandler.c
@@ -275,7 +275,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
u16 pm1_sts;
u32 smi_sts, gpe0_sts, tco_sts;
- pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc;
+ pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc;
printk(BIOS_SPEW, "SMI#: pmbase = 0x%04x\n", pmbase);
/* We need to clear the SMI status registers, or we won't see what's
@@ -325,7 +325,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
if (tco_sts & (1 << 8)) { // BIOSWR
u8 bios_cntl;
- bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+ bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) {
/* BWE is RW, so the SMI was caused by a
* write to BWE, not by a write to the BIOS
@@ -338,7 +338,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
* box.
*/
printk(BIOS_DEBUG, "Switching back to RO\n");
- pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
} /* No else for now? */
}
}
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index 8fc72b8..607cd14 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -168,8 +168,8 @@ int intel_early_me_init_done(u8 status)
} else if ((me_fws2 & 0x100) == 0x100) {
if ((me_fws2 & 0x80) == 0x80) {
printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n");
- reg16 = pcie_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80;
- pcie_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
+ reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80;
+ pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
set_global_reset(0);
outb(0x6, 0xcf9);
halt();
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 21a996d..cf0ea17 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -285,8 +285,8 @@ init_dmi (void)
void
early_pch_init_native (void)
{
- pcie_write_config8 (SOUTHBRIDGE, 0xa6,
- pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
+ pci_write_config8 (SOUTHBRIDGE, 0xa6,
+ pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
write32 (DEFAULT_RCBA + 0x2088, 0x00109000);
read32 (DEFAULT_RCBA + 0x20ac); // !!! = 0x00000000
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index aa9b5fc..81d3b6b 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -66,7 +66,7 @@ early_usb_init (const struct southbridge_usb_port *portmap)
for (i = 0; i < 22; i++)
write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0);
- pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
+ pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
/* Relock registers. */
outw (0x0000, DEFAULT_PMBASE | 0x003c);
diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c
index b81030d..6a8d6f1 100644
--- a/src/southbridge/intel/fsp_bd82x6x/finalize.c
+++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c
@@ -52,8 +52,8 @@ void intel_pch_finalize_smm(void)
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);
- pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
- pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
+ pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
+ pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
/* Indicate finalize step with post code */
outb(POST_OS_BOOT, 0x80);
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index a951f9f..a634134 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -496,14 +496,14 @@ static void intel_me7_finalize_smm(void)
u32 reg32;
mei_base_address = (u32 *)
- (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
- reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+ reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
memcpy(&hfs, ®32, sizeof(u32));
/* Abort and leave device alone if not normal mode */
@@ -516,10 +516,10 @@ static void intel_me7_finalize_smm(void)
mkhi_end_of_post();
/* Make sure IO is disabled */
- reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
+ reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
+ pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
/* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
@@ -527,7 +527,7 @@ static void intel_me7_finalize_smm(void)
void intel_me_finalize_smm(void)
{
- u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
+ u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
switch (did) {
case 0x1c3a8086:
intel_me7_finalize_smm();
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index 0d3a01e..4001fb9 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -489,14 +489,14 @@ void intel_me8_finalize_smm(void)
u32 reg32;
mei_base_address = (u32 *)
- (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
- reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+ reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
memcpy(&hfs, ®32, sizeof(u32));
/* Abort and leave device alone if not normal mode */
@@ -509,10 +509,10 @@ void intel_me8_finalize_smm(void)
mkhi_end_of_post();
/* Make sure IO is disabled */
- reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
+ reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
+ pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
/* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
index 01ace59..19337e9 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
@@ -279,7 +279,7 @@ static void southbridge_gate_memory_reset(void)
u32 reg32;
u16 gpiobase;
- gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
+ gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
if (!gpiobase)
return;
@@ -361,13 +361,13 @@ static void southbridge_smi_sleep(void)
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
*/
- reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
if (s5pwr == MAINBOARD_POWER_ON) {
reg8 &= ~1;
} else {
reg8 |= 1;
}
- pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
@@ -588,7 +588,7 @@ static void southbridge_smi_tco(void)
if (tco_sts & (1 << 8)) { // BIOSWR
u8 bios_cntl;
- bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+ bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) {
/* BWE is RW, so the SMI was caused by a
@@ -602,7 +602,7 @@ static void southbridge_smi_tco(void)
* box.
*/
printk(BIOS_DEBUG, "Switching back to RO\n");
- pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
} /* No else for now? */
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
/* Handle TCO timeout */
@@ -729,7 +729,7 @@ void southbridge_smi_handler(void)
u32 smi_sts;
/* Update global variable pmbase */
- pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
diff --git a/src/southbridge/intel/fsp_i89xx/finalize.c b/src/southbridge/intel/fsp_i89xx/finalize.c
index b81030d..6a8d6f1 100644
--- a/src/southbridge/intel/fsp_i89xx/finalize.c
+++ b/src/southbridge/intel/fsp_i89xx/finalize.c
@@ -52,8 +52,8 @@ void intel_pch_finalize_smm(void)
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);
- pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
- pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
+ pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
+ pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
/* Indicate finalize step with post code */
outb(POST_OS_BOOT, 0x80);
diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c
index 7ea42d4..704f209 100644
--- a/src/southbridge/intel/fsp_i89xx/me.c
+++ b/src/southbridge/intel/fsp_i89xx/me.c
@@ -463,14 +463,14 @@ static void intel_me7_finalize_smm(void)
u32 reg32;
mei_base_address = (u32 *)
- (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
- reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+ reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
memcpy(&hfs, ®32, sizeof(u32));
/* Abort and leave device alone if not normal mode */
@@ -483,10 +483,10 @@ static void intel_me7_finalize_smm(void)
mkhi_end_of_post();
/* Make sure IO is disabled */
- reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
+ reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
+ pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
/* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
@@ -494,7 +494,7 @@ static void intel_me7_finalize_smm(void)
void intel_me_finalize_smm(void)
{
- u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
+ u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
switch (did) {
case 0x1c3a8086:
intel_me7_finalize_smm();
diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c
index f25843e..b68a5dc 100644
--- a/src/southbridge/intel/fsp_i89xx/me_8.x.c
+++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c
@@ -458,14 +458,14 @@ void intel_me8_finalize_smm(void)
u32 reg32;
mei_base_address = (u32 *)
- (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
- reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+ reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
memcpy(&hfs, ®32, sizeof(u32));
/* Abort and leave device alone if not normal mode */
@@ -478,10 +478,10 @@ void intel_me8_finalize_smm(void)
mkhi_end_of_post();
/* Make sure IO is disabled */
- reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
+ reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
+ pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
/* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c
index d4dbb22..099fb84 100644
--- a/src/southbridge/intel/fsp_i89xx/smihandler.c
+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c
@@ -279,7 +279,7 @@ static void southbridge_gate_memory_reset(void)
u32 reg32;
u16 gpiobase;
- gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
+ gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
if (!gpiobase)
return;
@@ -361,13 +361,13 @@ static void southbridge_smi_sleep(void)
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
*/
- reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
if (s5pwr == MAINBOARD_POWER_ON) {
reg8 &= ~1;
} else {
reg8 |= 1;
}
- pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
@@ -588,7 +588,7 @@ static void southbridge_smi_tco(void)
if (tco_sts & (1 << 8)) { // BIOSWR
u8 bios_cntl;
- bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+ bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) {
/* BWE is RW, so the SMI was caused by a
@@ -602,7 +602,7 @@ static void southbridge_smi_tco(void)
* box.
*/
printk(BIOS_DEBUG, "Switching back to RO\n");
- pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
} /* No else for now? */
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
/* Handle TCO timeout */
@@ -726,7 +726,7 @@ void southbridge_smi_handler(void)
u32 smi_sts;
/* Update global variable pmbase */
- pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
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