[coreboot-gerrit] Patch set updated for coreboot: soc/intel/broadwell: add GPLD ACPI method

[Matt DeVillier (matt.devillier@gmail.com)]

Matt DeVillier (matt.devillier at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17542

-gerrit

commit 79969470b62b818a8f53e3be00723754aaa0697c
Author: CoolStar <coolstarorganization at gmail.com>
Date:   Fri Jul 15 13:55:19 2016 -0700

    soc/intel/broadwell: add GPLD ACPI method
    
    Add GPLD method for generating port location data (_PLD) for USB ports.
    This will be used by board-specific ACPI USB port definitions
    
    Change-Id: I7b153033a737ecad5dccf0695e253b0a53dd7944
    Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
 src/soc/intel/broadwell/acpi/xhci.asl | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl
index e9be16c..e3ffd6c 100644
--- a/src/soc/intel/broadwell/acpi/xhci.asl
+++ b/src/soc/intel/broadwell/acpi/xhci.asl
@@ -355,6 +355,19 @@ Device (XHCI)
 	{
 		Name (_ADR, 0x00000000)
 
+		Method (GPLD, 2, Serialized) {
+			Name (PCKG, Package (0x01) {
+				Buffer (0x10) {}
+			})
+			CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
+			Store (One, REV)
+			CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
+			Store (Arg0, VISI)
+			CreateField (DerefOf (Index (PCKG, Zero)), 0x57, 0x08, GPOS)
+			Store (Arg1, GPOS)
+			Return (PCKG)
+		}
+
 		// How many are there?
 		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
 		Device (PRT2) { Name (_ADR, 2) } // USB Port 1