[coreboot-gerrit] New patch to review for coreboot: soc/intel/broadwell: enumerate mising USB ports in ACPI
Matt DeVillier (matt.devillier@gmail.com)
gerrit at coreboot.org
Sun Nov 20 21:02:58 CET 2016
Matt DeVillier (matt.devillier at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17541
-gerrit
commit ab6963d21ace5d351f80339cc021a4b08eba6e7c
Author: CoolStar <coolstarorganization at gmail.com>
Date: Sun Aug 14 13:21:24 2016 -0700
soc/intel/broadwell: enumerate mising USB ports in ACPI
Broadwell supports up to 8 ECHI ports and 4 XHCI ports. Enumerate missing
port names to enable addition of board-specific details for each port.
Change-Id: I9f154a6f138934a862036d7af4400d491727f4a7
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
src/soc/intel/broadwell/acpi/xhci.asl | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl
index a70ded9..e9be16c 100644
--- a/src/soc/intel/broadwell/acpi/xhci.asl
+++ b/src/soc/intel/broadwell/acpi/xhci.asl
@@ -362,5 +362,11 @@ Device (XHCI)
Device (PRT4) { Name (_ADR, 4) } // USB Port 3
Device (PRT5) { Name (_ADR, 5) } // USB Port 4
Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+ Device (PRT7) { Name (_ADR, 7) } // USB Port 6
+ Device (PRT8) { Name (_ADR, 8) } // USB Port 7
+ Device (SSP1) { Name (_ADR, 10) }
+ Device (SSP2) { Name (_ADR, 11) }
+ Device (SSP3) { Name (_ADR, 12) }
+ Device (SSP4) { Name (_ADR, 13) }
}
}
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