[coreboot-gerrit] New patch to review for coreboot: AMD binaryPI: Disable PCI_CFG_EXT_IO

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17536

-gerrit

commit f13fc8896dff596cc9c61fca458f198d43399f25
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sun Nov 20 17:31:58 2016 +0200

    AMD binaryPI: Disable PCI_CFG_EXT_IO
    
    We don't need to do explicit pci_io_read/write operations,
    but can use MMCONF everywhere.
    
    Change-Id: Ib08028bda1b5226bb3b6b67e91f514480a9fc5ee
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/amd/pi/00630F01/Kconfig | 1 -
 src/cpu/amd/pi/00630F01/fixme.c | 7 -------
 src/cpu/amd/pi/00660F01/Kconfig | 1 -
 src/cpu/amd/pi/00660F01/fixme.c | 7 -------
 src/cpu/amd/pi/00670F00/Kconfig | 1 -
 src/cpu/amd/pi/00670F00/fixme.c | 7 -------
 src/cpu/amd/pi/00730F01/Kconfig | 1 -
 src/cpu/amd/pi/00730F01/fixme.c | 7 -------
 8 files changed, 32 deletions(-)

diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig
index 5b61a82..5c12ab6 100644
--- a/src/cpu/amd/pi/00630F01/Kconfig
+++ b/src/cpu/amd/pi/00630F01/Kconfig
@@ -15,7 +15,6 @@
 
 config CPU_AMD_PI_00630F01
 	bool
-	select PCI_IO_CFG_EXT
 	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
index d85f394..fcdc925 100644
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -72,13 +72,6 @@ void amd_initmmio(void)
 	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
 	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
 
-	/*
-	  Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
-	*/
-	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
-	MsrReg = MsrReg | 0x0000400000000000;
-	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig
index a556ecc..b38ea6c 100644
--- a/src/cpu/amd/pi/00660F01/Kconfig
+++ b/src/cpu/amd/pi/00660F01/Kconfig
@@ -15,7 +15,6 @@
 
 config CPU_AMD_PI_00660F01
 	bool
-	select PCI_IO_CFG_EXT
 	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index 9a38bd8..6770287 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -74,13 +74,6 @@ void amd_initmmio(void)
 	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
 	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
 
-	/*
-	  Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
-	*/
-	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
-	MsrReg = MsrReg | 0x0000400000000000;
-	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
 	/* For serial port */
 	PciData = 0xFF03FFD5;
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
diff --git a/src/cpu/amd/pi/00670F00/Kconfig b/src/cpu/amd/pi/00670F00/Kconfig
index 132d7e8..e47dfa3 100644
--- a/src/cpu/amd/pi/00670F00/Kconfig
+++ b/src/cpu/amd/pi/00670F00/Kconfig
@@ -15,7 +15,6 @@
 
 config CPU_AMD_PI_00670F00
 	bool
-	select PCI_IO_CFG_EXT
 	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c
index f892af8..86f5acf 100644
--- a/src/cpu/amd/pi/00670F00/fixme.c
+++ b/src/cpu/amd/pi/00670F00/fixme.c
@@ -77,13 +77,6 @@ void amd_initmmio(void)
 		(LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
 	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
 
-	/*
-	  Set the NB_CFG MSR register. Enable CF8 extended config cycles.
-	*/
-	LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
-	MsrReg = MsrReg | 0x0000400000000000;
-	LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
-
 	/* For serial port */
 	PciData = 0xFF03FFD5;
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44);
diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig
index baf7549..83af181 100644
--- a/src/cpu/amd/pi/00730F01/Kconfig
+++ b/src/cpu/amd/pi/00730F01/Kconfig
@@ -15,7 +15,6 @@
 
 config CPU_AMD_PI_00730F01
 	bool
-	select PCI_IO_CFG_EXT
 	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
index e16a4c4..fcdf498 100644
--- a/src/cpu/amd/pi/00730F01/fixme.c
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -74,13 +74,6 @@ void amd_initmmio(void)
 	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
 	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
 
-	/*
-	  Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
-	*/
-	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
-	MsrReg = MsrReg | 0x0000400000000000;
-	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
 	/* For serial port */
 	PciData = 0xFF03FFD5;
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);