[coreboot-gerrit] New patch to review for coreboot: mainboard/reef: Shrink RW_MRC_CACHE to fit only one item

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17498

-gerrit

commit 8b0fb3586019a2d350392e86e1a76be424c5984d
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Fri Nov 18 16:18:15 2016 -0800

    mainboard/reef: Shrink RW_MRC_CACHE to fit only one item
    
    Now that variable and constant MRC cache are separated MRC cache stays
    static. Static cache is not to change unless memory is retrained from
    scratch. As result multiple cache entries are not required.
    
    Shrink RW_MRC_CACHE so that it is large enough to fit only one cache
    dataset, and update other sections offsets accordingly.
    
    Change-Id: I3565757987ca7c5d5788d3b76a9cdfbe2e216f2d
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/mainboard/google/reef/chromeos.fmd | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd
index c7e51ee..9a470fa 100644
--- a/src/mainboard/google/reef/chromeos.fmd
+++ b/src/mainboard/google/reef/chromeos.fmd
@@ -12,31 +12,31 @@ FLASH 16M {
 			RO_UNUSED at 0x1bc000 0x40000
 		}
 	}
-	MISC_RW at 0x400000 0x4a000 {
-		UNIFIED_MRC_CACHE at 0x0 0x40000 {
+	MISC_RW at 0x400000 0x2b000 {
+		UNIFIED_MRC_CACHE at 0x0 0x21000 {
 			RECOVERY_MRC_CACHE at 0x0 0x10000
-			RW_MRC_CACHE at 0x10000 0x2f000
-			RW_VAR_MRC_CACHE at 0x3f000 0x1000
+			RW_MRC_CACHE at 0x10000 0x10000
+			RW_VAR_MRC_CACHE at 0x20000 0x1000
 		}
-		RW_ELOG at 0x40000 0x4000
-		RW_SHARED at 0x44000 0x4000 {
+		RW_ELOG at 0x21000 0x4000
+		RW_SHARED at 0x25000 0x4000 {
 			SHARED_DATA at 0x0 0x2000
 			VBLOCK_DEV at 0x2000 0x2000
 		}
-		RW_VPD at 0x48000 0x2000
+		RW_VPD at 0x29000 0x2000
 	}
-	RW_SECTION_A at 0x44a000 0x477800 {
+	RW_SECTION_A at 0x42b000 0x477800 {
 		VBLOCK_A at 0x0 0x10000
 		FW_MAIN_A(CBFS)@0x10000 0x4677c0
 		RW_FWID_A at 0x4777c0 0x40
 	}
-	RW_SECTION_B at 0x8c1800 0x477800 {
+	RW_SECTION_B at 0x8a2800 0x477800 {
 		VBLOCK_B at 0x0 0x10000
 		FW_MAIN_B(CBFS)@0x10000 0x4677c0
 		RW_FWID_B at 0x4777c0 0x40
 	}
-	RW_NVRAM at 0xd39000 0x6000
-	RW_LEGACY(CBFS)@0xd3f000 0x200000
+	RW_NVRAM at 0xd1a000 0x6000
+	RW_LEGACY(CBFS)@0xd20000 0x200000
 	BIOS_UNUSABLE at 0xf3f000 0x40000
 	DEVICE_EXTENSION at 0xf7f000 0x80000
 	# Currently, it is required that the BIOS region be a multiple of 8KiB.