[coreboot-gerrit] New patch to review for coreboot: mainboard/ms7721: Support for MSI MS-7721 (FM2-A75MA-E35) motherboard.
Renze Nicolai (renze@rnplus.nl)
gerrit at coreboot.org
Fri Nov 18 23:40:42 CET 2016
Renze Nicolai (renze at rnplus.nl) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17495
-gerrit
commit 70b7c6f76b75824d1c3536a7ffe0e6b410a7c5f1
Author: Renze Nicolai <renze at rnplus.nl>
Date: Fri Nov 18 23:33:16 2016 +0100
mainboard/ms7721: Support for MSI MS-7721 (FM2-A75MA-E35) motherboard.
Adds support for the MSI MS-7721 (FM2-A75MA-E35) motherboard.
Change-Id: I757e011de01ca9f340fd524b10e7fa3f291d53e3
Signed-off-by: Renze Nicolai <renze at rnplus.nl>
---
src/mainboard/msi/ms7721/BiosCallOuts.c | 40 +-
src/mainboard/msi/ms7721/Kconfig | 32 +-
src/mainboard/msi/ms7721/OemCustomize.c | 23 +-
src/mainboard/msi/ms7721/buildOpts.c | 9 +-
src/mainboard/msi/ms7721/cmos.layout | 2 +-
src/mainboard/msi/ms7721/devicetree.cb | 99 +-
src/mainboard/msi/ms7721/dsdt.asl | 44 +-
src/mainboard/msi/ms7721/dsdt.asl_vendor | 7165 ++++++++++++++++++++++++++++++
src/mainboard/msi/ms7721/irq_tables.c | 1 +
src/mainboard/msi/ms7721/mptable.c | 2 +-
src/mainboard/msi/ms7721/romstage.c | 172 +-
11 files changed, 7434 insertions(+), 155 deletions(-)
diff --git a/src/mainboard/msi/ms7721/BiosCallOuts.c b/src/mainboard/msi/ms7721/BiosCallOuts.c
index 98bb067..72bf7eb 100644
--- a/src/mainboard/msi/ms7721/BiosCallOuts.c
+++ b/src/mainboard/msi/ms7721/BiosCallOuts.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Renze Nicolai <renze at rnplus.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -37,32 +38,31 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
/**
- * ASUS F2A85-M board ALC887-VD Verb Table
+ * MSI MS-7721 board ALC887-VD Verb Table
*
- * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
+ * Copied from `/sys/class/sound/hwC1D3/init_pin_configs` when running
* the vendor BIOS.
*/
-const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
- {0x11, 0x99430140},
- {0x12, 0x411111f0},
- {0x14, 0x01014010},
- {0x15, 0x01011012},
- {0x16, 0x01016011},
- {0x17, 0x01012014},
- {0x18, 0x01a19850},
- {0x19, 0x02a19c60},
- {0x1a, 0x0181305f},
- {0x1b, 0x02214c20},
- {0x1c, 0x411111f0},
- {0x1d, 0x4005e601},
- {0x1e, 0x01456130},
- {0x1f, 0x411111f0},
- {0xff, 0xffffffff}
+const CODEC_ENTRY ms7721_alc887_VerbTbl[] = {
+{0x11, 0x411111f0},
+{0x12, 0x411111f0},
+{0x14, 0x01014410},
+{0x15, 0x01011412},
+{0x16, 0x01016411},
+{0x17, 0x01012414},
+{0x18, 0x01a19c30},
+{0x19, 0x02a19c40},
+{0x1a, 0x0181343f},
+{0x1b, 0x02214c20},
+{0x1c, 0x411111f0},
+{0x1d, 0x4007f603},
+{0x1e, 0x411111f0},
+{0x1f, 0x411111f0}
};
static const CODEC_TBL_LIST CodecTableList[] =
{
- {0x10ec0887, (CODEC_ENTRY*)&f2a85_m_alc887_VerbTbl[0]},
+ {0x10ec0887, (CODEC_ENTRY*)&ms7721_alc887_VerbTbl[0]},
{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
};
@@ -97,7 +97,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_env->Usb.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
}
- printk(BIOS_DEBUG, "Done\n");
+ printk(BIOS_DEBUG, "Done.\n");
return AGESA_SUCCESS;
}
diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig
index 138ca34..7a2623b 100644
--- a/src/mainboard/msi/ms7721/Kconfig
+++ b/src/mainboard/msi/ms7721/Kconfig
@@ -3,6 +3,8 @@
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
# Copyright (C) 2012 Rudolf Marek <r.marek at assembler.cz>
+# Copyright (C) 2016 Renze Nicolai <renze at rnplus.nl>
+
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -25,35 +27,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
- select SUPERIO_ITE_IT8728F
+ select SUPERIO_FINTEK_F71869AD
select BOARD_ROMSIZE_KB_8192
select GFXUMA
select HUDSON_DISABLE_IMC
-choice
- prompt "DDR3 memory voltage"
- default BOARD_MSI_MS7721_DDR3_VOLT_150
-
-config BOARD_MSI_MS7721_DDR3_VOLT_135
- bool "1.35V"
- help
- Set DRR3 memory voltage to 1.35V
-config BOARD_MSI_MS7721_DDR3_VOLT_150
- bool "1.50V"
- help
- Set DRR3 memory voltage to 1.50V
-config BOARD_MSI_MS7721_DDR3_VOLT_165
- bool "1.65V"
- help
- Set DRR3 memory voltage to 1.65V
-endchoice
-
-config BOARD_MSI_MS7721_DDR3_VOLT_VAL
- hex
- default 0x9e if BOARD_MSI_MS7721_DDR3_VOLT_135
- default 0x0 if BOARD_MSI_MS7721_DDR3_VOLT_150
- default 0x1e if BOARD_MSI_MS7721_DDR3_VOLT_165
-
config MAINBOARD_DIR
string
default msi/ms7721
@@ -92,11 +70,11 @@ config ONBOARD_VGA_IS_PRIMARY
config VGA_BIOS_ID
string
- default "1002,9993"
+ default "1002,990e"
config HUDSON_LEGACY_FREE
bool
- default y
+ default n
config POST_IO
bool
diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c
index a6c9833..368e340 100644
--- a/src/mainboard/msi/ms7721/OemCustomize.c
+++ b/src/mainboard/msi/ms7721/OemCustomize.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Renze Nicolai <renze at rnplus.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -69,18 +70,30 @@
*/
static const PCIe_PORT_DESCRIPTOR PortList [] = {
- /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
+ /* PCIe port, Lanes 8:23, PCI Device Number 2, x16 slot */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
- /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
+ /* PCIe port, Lane 4, PCI Device Number 4, Realtek LAN */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
+ /* PCIe port, Lane 5, PCI Device Number 5, x1 slot (1) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+ /* PCIe port, Lane 6, PCI Device Number 6, x1 slot (2) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
{
DESCRIPTOR_TERMINATE_LIST,
@@ -92,8 +105,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/*
* It is not known, if the setup is complete.
*
- * Tested and works: VGA/DVI
- * Untested: HDMI
+ * Tested and works: VGA, HDMI
+ * Untested: DVI
*/
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
// DP0 to HDMI0/DP
diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c
index e0a1ea4..59d66ae 100644
--- a/src/mainboard/msi/ms7721/buildOpts.c
+++ b/src/mainboard/msi/ms7721/buildOpts.c
@@ -43,13 +43,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the CPU family. */
+/* Select the cpu family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the CPU socket type. */
+/* Select the cpu socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
@@ -326,11 +326,11 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
//#define FCH_NO_XHCI_SUPPORT FALSE
-GPIO_CONTROL f2a85_m_gpio[] = {
+GPIO_CONTROL ms7721_m_gpio[] = {
// {183, Function1, PullUpB},
{-1}
};
-#define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0])
+#define BLDCFG_FCH_GPIO_CONTROL_LIST (&ms7721_m_gpio[0])
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
@@ -345,3 +345,4 @@ GPIO_CONTROL f2a85_m_gpio[] = {
/* Moving this include up will break AGESA. */
#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
+
diff --git a/src/mainboard/msi/ms7721/cmos.layout b/src/mainboard/msi/ms7721/cmos.layout
index 75a2d30..d83bb14 100644
--- a/src/mainboard/msi/ms7721/cmos.layout
+++ b/src/mainboard/msi/ms7721/cmos.layout
@@ -18,7 +18,7 @@ entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
-388 4 h 0 reboot_counter
+388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb
index 6b728d5..09eaa79 100644
--- a/src/mainboard/msi/ms7721/devicetree.cb
+++ b/src/mainboard/msi/ms7721/devicetree.cb
@@ -2,6 +2,7 @@
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2016 Renze Nicolai <renze at rnplus.nl>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -27,25 +28,25 @@ chip northbridge/amd/agesa/family15tn/root_complex
chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU
- device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x990e
device pci 1.1 on end # Internal Multimedia
- device pci 2.0 on end # PCIE SLOT0 x16 blue
- device pci 3.0 off end # unused?
- device pci 4.0 on end # PCIE 4x black
- device pci 5.0 off end # unused?
- device pci 6.0 off end # unused?
+ device pci 2.0 on end # PCIe x16
+ device pci 3.0 off end # -
+ device pci 4.0 on end # PCIE Realtek LAN
+ device pci 5.0 on end # PCIE x1 (1)
+ device pci 6.0 on end # PCIE x1 (2)
device pci 7.0 off end # LAN
device pci 8.0 off end # NB/SB Link P2P bridge
end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
- device pci 10.0 on end # XHCI HC0
- device pci 10.1 on end # XHCI HC1
+ device pci 10.0 on end # USB XHCI
+ device pci 10.1 on end # USB XHCI
device pci 11.0 on end # SATA
- device pci 12.0 on end # USB
- device pci 12.2 on end # USB
- device pci 13.0 on end # USB
- device pci 13.2 on end # USB
+ device pci 12.0 on end # USB OHCI
+ device pci 12.2 on end # USB EHCI
+ device pci 13.0 on end # USB OHCI
+ device pci 13.2 on end # USB EHCI
device pci 14.0 on # SMBUS
chip drivers/generic/generic #dimm 0
device i2c 50 on end # 7-bit SPD address
@@ -55,61 +56,65 @@ chip northbridge/amd/agesa/family15tn/root_complex
end
end # SM
device pci 14.1 off end # IDE 0x439c
- device pci 14.2 on end # HDA 0x4383
+ device pci 14.2 on end # Azallia (Audio)
device pci 14.3 on # LPC 0x439d
- chip superio/ite/it8728f
- register hwm_ctl_register = "0xc0"
- register hwm_main_ctl_register = "0x33"
- register hwm_adc_temp_chan_en_reg = "0x38"
- register hwm_fan1_ctl_pwm = "0x00"
- register hwm_fan2_ctl_pwm = "0x00"
- register hwm_fan3_ctl_pwm = "0x00"
+ chip superio/fintek/f71869ad
+ register "multi_function_register_1" = "0x01"
+ register "multi_function_register_2" = "0x0f"
+ register "multi_function_register_3" = "0x2f"
+ register "multi_function_register_4" = "0x04"
+ register "multi_function_register_5" = "0x3e"
- device pnp 2e.0 off # Floppy
+ # HWM configuration registers
+ register "hwm_smbus_address" = "0x98"
+ register "hwm_smbus_control_reg" = "0x02"
+ register "hwm_fan_type_sel_reg" = "0x00"
+ register "hwm_fan1_temp_adj_rate_reg" = "0x33"
+ register "hwm_fan_mode_sel_reg" = "0x07"
+ register "hwm_fan1_idx_rpm_mode" = "0x0e"
+ register "hwm_fan1_seg1_speed_count" = "0xff"
+ register "hwm_fan1_seg2_speed_count" = "0x0e"
+ register "hwm_fan1_seg3_speed_count" = "0x07"
+ register "hwm_fan1_temp_map_sel" = "0x8c"
+ device pnp 4e.00 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
- device pnp 2e.1 on # Com1
+ device pnp 4e.01 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 2e.2 off # Com2
+ device pnp 4e.02 off # COM2 (not physically wired on board!)
io 0x60 = 0x2f8
irq 0x70 = 3
end
- device pnp 2e.3 off # Parallel Port
+ device pnp 4e.03 on # Parallel Port
io 0x60 = 0x378
- irq 0x70 = 7
+ irq 0x70 = 5
+ drq 0x74 = 3
end
- device pnp 2e.4 on # Env Controller
- io 0x60 = 0x290
- io 0x62 = 0x220
+ device pnp 4e.04 on # Hardware Monitor
+ io 0x60 = 0x600
irq 0x70 = 0
end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
+ device pnp 4e.05 on # KBC
+ io 0x60 = 0x060
+ irq 0x70 = 1 # Keyboard IRQ
+ irq 0x72 = 12 # Mouse IRQ
end
- device pnp 2e.6 off # Mouse
- irq 0x70 = 12
- end
- device pnp 2e.7 on # GPIO
- io 0x60 = 0x228 #SMI
- io 0x62 = 0x300 #Simple I/O
- io 0x64 = 0x238 #Phony resource IT8603E does not have it
- irq 0x70 = 0
- end
- device pnp 2e.a off end # CIR
- end #superio/ite/it8728f
+ device pnp 4e.06 on end # GPIO
+ device pnp 4e.07 on end # WDT
+ device pnp 4e.08 off end # CIR
+ device pnp 4e.0a on end # PME
+ end # f71869ad
end #device pci 14.3 # LPC
- device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # USB 2
+ device pci 14.4 on end # PCI 0x4384 (PCI slot on board)
+ device pci 14.5 on end # USB OHCI
device pci 14.6 off end # Gec
device pci 14.7 off end # SD
- device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
- device pci 15.1 on end # PCIe 1 onboard gigabit
+ device pci 15.0 off end # unused
+ device pci 15.1 off end # PCIe 1 onboard gigabit
device pci 15.2 off end # unused
device pci 15.3 off end # unused
diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl
index f022d4d..1b32f63 100644
--- a/src/mainboard/msi/ms7721/dsdt.asl
+++ b/src/mainboard/msi/ms7721/dsdt.asl
@@ -3,6 +3,7 @@
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
+ * Copyright (C) 2016 Renze Nicolai <renze at rnplus.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,18 +20,18 @@ DefinitionBlock (
"DSDT.AML", /* Output filename */
"DSDT", /* Signature */
0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "ASUS ", /* OEMID */
+ "MSI", /* OEMID */
"COREBOOT", /* TABLE ID */
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+ #include <arch/x86/acpi/debug.asl> /* Include global debug methods if needed */
/* Globals for the platform */
#include "acpi/mainboard.asl"
/* Describe the USB Overcurrent pins */
- #include "acpi/usb_oc.asl"
+ //#include "acpi/usb_oc.asl"
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
@@ -69,28 +70,31 @@ DefinitionBlock (
* TODO: The devices listed here (SBR0 and SBR1) do not appear to
* be referenced anywhere and could possibly be removed.
*/
- Device(SBR0) { /* PCIe 1x SB */
- Name(_ADR, 0x00150000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(ABR0) } /* APIC mode */
- Return (PBR0) /* PIC mode */
- }
- }
-
- Device(SBR1) { /* Onboard network */
- Name(_ADR, 0x00150001)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT, 0) {
- If(PMOD){ Return(ABR1) } /* APIC mode */
- Return (PBR1) /* PIC mode */
- }
- }
+ //Device(SBR0) { /* PCIe 1x SB */
+ // Name(_ADR, 0x00150000)
+ // Name(_PRW, Package() {0x18, 4})
+ // Method(_PRT,0) {
+ // If(PMOD){ Return(ABR0) } /* APIC mode */
+ // Return (PBR0) /* PIC mode */
+ // }
+ //}
+
+ //Device(SBR1) { /* Onboard network */
+ // Name(_ADR, 0x00150001)
+ // Name(_PRW, Package() {0x18, 4})
+ // Method(_PRT, 0) {
+ // If(PMOD){ Return(ABR1) } /* APIC mode */
+ // Return (PBR1) /* PIC mode */
+ // }
+ //}
}
/* Describe PCI INT[A-H] for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+ /* Describe USB for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/usb.asl>
+
} /* End Scope(_SB) */
/* Describe SMBUS for the Southbridge */
diff --git a/src/mainboard/msi/ms7721/dsdt.asl_vendor b/src/mainboard/msi/ms7721/dsdt.asl_vendor
new file mode 100644
index 0000000..c80c25a
--- /dev/null
+++ b/src/mainboard/msi/ms7721/dsdt.asl_vendor
@@ -0,0 +1,7165 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20160212-64
+ * Copyright (c) 2000 - 2016 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of dsdt.dat, Thu Jun 30 14:07:45 2016
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x000060C3 (24771)
+ * Revision 0x02
+ * Checksum 0xD9
+ * OEM ID "ALASKA"
+ * OEM Table ID "A M I"
+ * OEM Revision 0x00000000 (0)
+ * Compiler ID "INTL"
+ * Compiler Version 0x20051117 (537202967)
+ */
+DefinitionBlock ("dsdt.aml", "DSDT", 2, "ALASKA", "A M I", 0x00000000)
+{
+
+ External (APTS, MethodObj) // 1 Arguments
+ External (AWAK, MethodObj) // 1 Arguments
+
+ Name (SP1O, 0x4E)
+ Name (IO1B, 0x0A00)
+ Name (IO1L, 0x20)
+ Name (IO2B, 0x0600)
+ Name (IO2L, 0x10)
+ Name (IO3B, Zero)
+ Name (IO3L, Zero)
+ Name (PEBS, 0xE0000000)
+ Name (PEBL, 0x10000000)
+ Name (PXNO, 0x02)
+ Name (SMBB, 0x0B20)
+ Name (SMBL, 0x20)
+ Name (SMB0, 0x0B00)
+ Name (SMBM, 0x10)
+ Name (PMBS, 0x0800)
+ Name (PMLN, 0xA0)
+ Name (SMIO, 0xB2)
+ Name (GPBS, Zero)
+ Name (GPLN, Zero)
+ Name (APCB, 0xFEC00000)
+ Name (APCL, 0x1000)
+ Name (SPIB, 0xFEC10000)
+ Name (SPIL, 0x1000)
+ Name (HPTB, 0xFED00000)
+ Name (HPTL, 0x1000)
+ Name (GIOB, 0xFED80100)
+ Name (IOMB, 0xFED80D00)
+ Name (SSMB, 0xFED80200)
+ Name (ACPH, 0xDE)
+ Name (ASSB, Zero)
+ Name (AOTB, Zero)
+ Name (AAXB, Zero)
+ Name (PEHP, One)
+ Name (SHPC, One)
+ Name (PEPM, One)
+ Name (PEER, One)
+ Name (ITKE, Zero)
+ Name (SRSI, 0xB2)
+ Name (CSMI, 0x61)
+ Name (SMIA, 0xB2)
+ Name (SMIB, 0xB3)
+ Name (OFST, 0x35)
+ Name (TRST, 0x02)
+ Name (TPMF, Zero)
+ Name (TCMF, Zero)
+ Name (TMF1, Zero)
+ Name (TMF2, Zero)
+ Name (TMF3, Zero)
+ Name (CPVD, One)
+ Name (HIDK, "MSFT0001")
+ Name (HIDM, "MSFT0003")
+ Name (CIDK, 0x0303D041)
+ Name (CIDM, 0x130FD041)
+ Name (ATIS, 0x55)
+ Name (MBEC, Zero)
+ Name (FESI, 0xDB)
+ Name (FDSI, 0xDC)
+ Name (FSSI, 0xD9)
+ Name (SMIP, 0xB2)
+ Name (CISI, 0x88)
+ Name (PECS, Zero)
+ Name (PICM, Zero)
+ Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
+ {
+ If (Arg0)
+ {
+ DBG8 = 0xAA
+ }
+ Else
+ {
+ DBG8 = 0xAC
+ }
+
+ PICM = Arg0
+ }
+
+ Name (OSVR, Ones)
+ Method (OSFL, 0, NotSerialized)
+ {
+ If ((OSVR != Ones))
+ {
+ Return (OSVR) /* \OSVR */
+ }
+
+ If ((PICM == Zero))
+ {
+ DBG8 = 0xAC
+ }
+
+ OSVR = 0x03
+ If (CondRefOf (_OSI, Local0))
+ {
+ If (_OSI ("Windows 2001"))
+ {
+ OSVR = 0x04
+ }
+
+ If (_OSI ("Windows 2001.1"))
+ {
+ OSVR = 0x05
+ }
+
+ If (_OSI ("FreeBSD"))
+ {
+ OSVR = 0x06
+ }
+
+ If (_OSI ("HP-UX"))
+ {
+ OSVR = 0x07
+ }
+
+ If (_OSI ("OpenVMS"))
+ {
+ OSVR = 0x08
+ }
+
+ If (_OSI ("Windows 2001 SP1"))
+ {
+ OSVR = 0x09
+ }
+
+ If (_OSI ("Windows 2001 SP2"))
+ {
+ OSVR = 0x0A
+ }
+
+ If (_OSI ("Windows 2001 SP3"))
+ {
+ OSVR = 0x0B
+ }
+
+ If (_OSI ("Windows 2006"))
+ {
+ OSVR = 0x0C
+ }
+
+ If (_OSI ("Windows 2006 SP1"))
+ {
+ OSVR = 0x0D
+ }
+
+ If (_OSI ("Windows 2009"))
+ {
+ OSVR = 0x0E
+ }
+
+ If (_OSI ("Windows 2012"))
+ {
+ OSVR = 0x0F
+ }
+ }
+ ElseIf (MCTH (_OS, "Microsoft Windows NT"))
+ {
+ OSVR = Zero
+ }
+
+ Return (OSVR) /* \OSVR */
+ }
+
+ Method (MCTH, 2, NotSerialized)
+ {
+ If ((SizeOf (Arg0) < SizeOf (Arg1)))
+ {
+ Return (Zero)
+ }
+
+ Local0 = (SizeOf (Arg0) + One)
+ Name (BUF0, Buffer (Local0) {})
+ Name (BUF1, Buffer (Local0) {})
+ BUF0 = Arg0
+ BUF1 = Arg1
+ While (Local0)
+ {
+ Local0--
+ If ((DerefOf (BUF0 [Local0]) != DerefOf (BUF1 [Local0]
+ )))
+ {
+ Return (Zero)
+ }
+ }
+
+ Return (One)
+ }
+
+ Name (PRWP, Package (0x02)
+ {
+ Zero,
+ Zero
+ })
+ Method (GPRW, 2, NotSerialized)
+ {
+ PRWP [Zero] = Arg0
+ Local0 = (SS1 << One)
+ Local0 |= (SS2 << 0x02)
+ Local0 |= (SS3 << 0x03)
+ Local0 |= (SS4 << 0x04)
+ If (((One << Arg1) & Local0))
+ {
+ PRWP [One] = Arg1
+ }
+ Else
+ {
+ Local0 >>= One
+ If (((OSFL () == One) || (OSFL () == 0x02)))
+ {
+ FindSetLeftBit (Local0, PRWP [One])
+ }
+ Else
+ {
+ FindSetRightBit (Local0, PRWP [One])
+ }
+ }
+
+ Return (PRWP) /* \PRWP */
+ }
+
+ Name (WAKP, Package (0x02)
+ {
+ Zero,
+ Zero
+ })
+ OperationRegion (DEB0, SystemIO, 0x80, One)
+ Field (DEB0, ByteAcc, NoLock, Preserve)
+ {
+ DBG8, 8
+ }
+
+ OperationRegion (DEB1, SystemIO, 0x90, 0x02)
+ Field (DEB1, WordAcc, NoLock, Preserve)
+ {
+ DBG9, 16
+ }
+
+ Name (SS1, Zero)
+ Name (SS2, Zero)
+ Name (SS3, One)
+ Name (SS4, One)
+ Name (IOST, 0x0005)
+ Name (TOPM, 0x00000000)
+ Name (ROMS, 0xFFE00000)
+ Name (VGAF, One)
+ OperationRegion (DEB2, SystemIO, 0x80, 0x02)
+ Field (DEB2, WordAcc, NoLock, Preserve)
+ {
+ P80H, 16
+ }
+
+ Name (OSTY, Ones)
+ OperationRegion (ACMS, SystemIO, 0x72, 0x10)
+ Field (ACMS, ByteAcc, NoLock, Preserve)
+ {
+ ICMS, 8,
+ DCMS, 8,
+ Offset (0x0E),
+ P80, 8
+ }
+
+ Name (PCIE, 0xE0000000)
+ Name (OSCF, Zero)
+ Name (GGN2, One)
+ OperationRegion (CMPT, SystemIO, 0x0C50, 0x03)
+ Field (CMPT, ByteAcc, NoLock, Preserve)
+ {
+ CMID, 8,
+ , 6,
+ GPCT, 2,
+ GP0I, 1,
+ GP1I, 1,
+ GP2I, 1,
+ GP3I, 1,
+ GP4I, 1,
+ GP5I, 1,
+ GP6I, 1,
+ GP7I, 1
+ }
+
+ OperationRegion (PCFG, SystemMemory, PCIE, 0x02000000)
+ Field (PCFG, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x20078),
+ Offset (0x2007A),
+ PMSA, 1,
+ Offset (0x28078),
+ Offset (0x2807A),
+ PMSB, 1,
+ Offset (0x48078),
+ Offset (0x4807A),
+ PMSC, 1,
+ Offset (0x8800A),
+ STCL, 16,
+ Offset (0x880FC),
+ RMBA, 32,
+ Offset (0xA0004),
+ SMIE, 1,
+ SMME, 1,
+ Offset (0xA0008),
+ RVID, 8,
+ Offset (0xA0014),
+ SMB1, 32,
+ Offset (0xA0082),
+ , 2,
+ G31O, 1,
+ Offset (0xA00E1),
+ , 6,
+ ACIR, 1,
+ Offset (0xA4004),
+ PCMD, 2,
+ Offset (0xA807A),
+ PMS0, 1,
+ Offset (0xA8088),
+ TLS0, 4,
+ Offset (0xA907A),
+ PMS1, 1,
+ Offset (0xA9088),
+ TLS1, 4,
+ Offset (0xAA07A),
+ PMS2, 1,
+ Offset (0xAA088),
+ TLS2, 4,
+ Offset (0xAB07A),
+ PMS3, 1,
+ Offset (0xAB088),
+ TLS3, 4
+ }
+
+ OperationRegion (PMIO, SystemIO, 0x0CD6, 0x02)
+ Field (PMIO, ByteAcc, NoLock, Preserve)
+ {
+ INPM, 8,
+ DAPM, 8
+ }
+
+ IndexField (INPM, DAPM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x24),
+ MMSO, 32,
+ Offset (0x50),
+ HPAD, 32,
+ Offset (0x60),
+ P1EB, 16
+ }
+
+ OperationRegion (ERMM, SystemMemory, MMSO, 0x1000)
+ Field (ERMM, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x105),
+ , 5,
+ G06E, 1,
+ G06O, 1,
+ G06I, 1,
+ G07B, 8,
+ Offset (0x10A),
+ G0BB, 8,
+ Offset (0x10D),
+ G0EB, 8,
+ Offset (0x113),
+ , 5,
+ G14E, 1,
+ G14O, 1,
+ G14I, 1,
+ , 5,
+ G15E, 1,
+ G15O, 1,
+ G15I, 1,
+ Offset (0x11B),
+ , 7,
+ G1CI, 1,
+ Offset (0x11F),
+ , 7,
+ G20I, 1,
+ Offset (0x122),
+ , 5,
+ G23E, 1,
+ G23O, 1,
+ G23I, 1,
+ Offset (0x12B),
+ , 5,
+ G2CE, 1,
+ G2CO, 1,
+ G2CI, 1,
+ , 5,
+ G2DE, 1,
+ G2DO, 1,
+ G2DI, 1,
+ Offset (0x132),
+ , 5,
+ G33E, 1,
+ G33O, 1,
+ G33I, 1,
+ Offset (0x134),
+ , 5,
+ G35E, 1,
+ G35O, 1,
+ Offset (0x136),
+ , 5,
+ G37E, 1,
+ G37O, 1,
+ G37I, 1,
+ Offset (0x13F),
+ , 7,
+ G40I, 1,
+ Offset (0x164),
+ , 7,
+ GE05, 1,
+ , 7,
+ GE06, 1,
+ Offset (0x16E),
+ , 7,
+ GE15, 1,
+ , 7,
+ GE16, 1,
+ Offset (0x175),
+ , 7,
+ GE22, 1,
+ Offset (0x1A9),
+ , 5,
+ GAAE, 1,
+ GAAO, 1,
+ GAAI, 1,
+ , 5,
+ GABE, 1,
+ GABO, 1,
+ Offset (0x1AE),
+ GAFB, 8,
+ GB0B, 8,
+ Offset (0x1FF),
+ , 9,
+ GESA, 1,
+ Offset (0x207),
+ , 5,
+ E05C, 1,
+ E06C, 1,
+ Offset (0x208),
+ E08C, 1,
+ E09C, 1,
+ Offset (0x209),
+ E10C, 1,
+ Offset (0x20A),
+ , 5,
+ E1DC, 1,
+ Offset (0x2AF),
+ , 2,
+ SLPS, 2,
+ Offset (0x376),
+ EPNM, 1,
+ DPPF, 1,
+ Offset (0x3BA),
+ , 6,
+ PWDE, 1,
+ Offset (0x3BD),
+ , 5,
+ ALLS, 1,
+ Offset (0x3EF),
+ PHYD, 1,
+ , 1,
+ , 1,
+ US5R, 1,
+ Offset (0x3F5),
+ GECD, 1,
+ Offset (0xD05),
+ G06M, 8,
+ G07M, 8,
+ Offset (0xD0A),
+ G0BM, 8,
+ Offset (0xD0D),
+ G0EM, 8,
+ Offset (0xD13),
+ G14M, 8,
+ Offset (0xD1B),
+ G1CM, 8,
+ Offset (0xD1F),
+ G20M, 8,
+ Offset (0xD22),
+ G23M, 8,
+ Offset (0xD2C),
+ G2DM, 8,
+ Offset (0xD36),
+ G37M, 8,
+ Offset (0xD6F),
+ G70M, 8,
+ Offset (0xD75),
+ G76M, 8,
+ Offset (0xDA9),
+ GAAM, 8,
+ Offset (0xDAE),
+ GAFM, 8,
+ GB0M, 8,
+ Offset (0xE7F),
+ , 2,
+ IMCS, 1
+ }
+
+ OperationRegion (ABIO, SystemIO, 0x0CD8, 0x08)
+ Field (ABIO, DWordAcc, NoLock, Preserve)
+ {
+ INAB, 32,
+ DAAB, 32
+ }
+
+ Method (RDAB, 1, NotSerialized)
+ {
+ INAB = Arg0
+ Return (DAAB) /* \DAAB */
+ }
+
+ Method (WTAB, 2, NotSerialized)
+ {
+ INAB = Arg0
+ DAAB = Arg1
+ }
+
+ Method (RWAB, 3, NotSerialized)
+ {
+ Local0 = (RDAB (Arg0) & Arg1)
+ Local1 = (Local0 | Arg2)
+ WTAB (Arg0, Local1)
+ }
+
+ Method (CABR, 3, NotSerialized)
+ {
+ Local0 = (Arg0 << 0x05)
+ Local1 = (Local0 + Arg1)
+ Local2 = (Local1 << 0x18)
+ Local3 = (Local2 + Arg2)
+ Return (Local3)
+ }
+
+ Method (GHPS, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ RWAB (CABR (0x06, Zero, 0xC0), 0xFFFFBFFF, Zero)
+ RWAB (CABR (One, Zero, 0x65), 0xFFFFFBFB, Zero)
+ Stall (0xC8)
+ }
+
+ If ((Arg0 == One))
+ {
+ RWAB (CABR (0x06, Zero, 0xC0), 0xFFFFBFFF, 0x4000)
+ RWAB (CABR (One, Zero, 0x65), 0xFFFFFBFB, 0x0404)
+ Stall (0xC8)
+ }
+
+ If (GGN2)
+ {
+ If ((Arg0 == Zero))
+ {
+ GEN2 ()
+ Local0 = RDAB (CABR (0x03, 0x02, 0xA5))
+ Local0 &= 0xFF
+ Local1 = 0x01F4
+ While (((Local1 > Zero) && (Local0 != 0x10)))
+ {
+ Local0 = RDAB (CABR (0x03, 0x02, 0xA5))
+ Local0 &= 0xFF
+ Local1--
+ Stall (0xC8)
+ Stall (0xC8)
+ }
+
+ If ((Local0 != 0x10))
+ {
+ GEN1 ()
+ }
+ }
+ }
+ }
+
+ Method (GEN2, 0, NotSerialized)
+ {
+ TLS2 = 0x02
+ RWAB (CABR (0x03, 0x02, 0xA4), 0xFFFFFFFE, One)
+ RWAB (CABR (0x03, 0x02, 0xA2), 0xFFFFDFFF, 0x2000)
+ RWAB (CABR (0x03, 0x02, 0xC0), 0xFFFF7FFF, 0x8000)
+ RWAB (CABR (0x03, 0x02, 0xA4), 0xDFFFFFFF, 0x20000000)
+ Stall (0xC8)
+ Stall (0xC8)
+ }
+
+ Method (GEN1, 0, NotSerialized)
+ {
+ TLS2 = One
+ RWAB (CABR (0x03, 0x02, 0xA4), 0xFFFFFFFE, Zero)
+ RWAB (CABR (0x03, 0x02, 0xA2), 0xFFFFDFFF, 0x2000)
+ Stall (0xC8)
+ Stall (0xC8)
+ }
+
+ OperationRegion (P1E0, SystemIO, P1EB, 0x04)
+ Field (P1E0, ByteAcc, NoLock, Preserve)
+ {
+ , 14,
+ PEWS, 1,
+ WSTA, 1,
+ , 14,
+ PEWD, 1
+ }
+
+ Method (SPTS, 1, NotSerialized)
+ {
+ PCMD = One
+ P80 = Arg0
+ If (IMCS)
+ {
+ IBSE ()
+ }
+
+ CPMS ()
+ CPMS ()
+ PEWS = One
+ }
+
+ Method (SWAK, 1, NotSerialized)
+ {
+ If (PICM)
+ {
+ \_SB.IRQC ()
+ }
+
+ CPMS ()
+ CPMS ()
+ PEWS = One
+ If (IMCS)
+ {
+ IBWE ()
+ }
+ }
+
+ Method (TRMD, 1, NotSerialized)
+ {
+ }
+
+ Method (CPMS, 0, NotSerialized)
+ {
+ If ((EPNM == Zero))
+ {
+ PMSA = One
+ PMSB = One
+ PMSC = One
+ PMS0 = One
+ PMS1 = One
+ PMS2 = One
+ PMS3 = One
+ }
+ }
+
+ Scope (_GPE)
+ {
+ }
+
+ OperationRegion (IMIO, SystemIO, 0x3E, 0x02)
+ Field (IMIO, ByteAcc, NoLock, Preserve)
+ {
+ IMCX, 8,
+ IMCA, 8
+ }
+
+ IndexField (IMCX, IMCA, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x80),
+ MSTI, 8,
+ MITS, 8,
+ MRG0, 8,
+ MRG1, 8,
+ MRG2, 8,
+ MRG3, 8
+ }
+
+ Method (WACK, 0, NotSerialized)
+ {
+ Local0 = Zero
+ While ((Local0 != 0xFA))
+ {
+ Local0 = MRG0 /* \MRG0 */
+ Sleep (0x0A)
+ }
+ }
+
+ Method (IBSE, 0, NotSerialized)
+ {
+ MRG0 = Zero
+ MRG1 = 0xB5
+ MRG2 = Zero
+ MSTI = 0x96
+ WACK ()
+ MRG0 = Zero
+ MRG1 = Zero
+ MRG2 = Zero
+ MSTI = 0x80
+ WACK ()
+ Local0 = MRG2 /* \MRG2 */
+ Local0 &= 0xFE
+ MRG0 = Zero
+ MRG1 = Zero
+ MRG2 = Local0
+ MSTI = 0x81
+ WACK ()
+ MRG0 = Zero
+ MRG1 = One
+ MRG2 = Zero
+ MSTI = 0x98
+ WACK ()
+ MRG0 = Zero
+ MRG1 = 0xB4
+ MRG2 = Zero
+ MSTI = 0x96
+ WACK ()
+ }
+
+ Method (IBWE, 0, NotSerialized)
+ {
+ MRG0 = Zero
+ MRG1 = 0xB5
+ MRG2 = Zero
+ MSTI = 0x96
+ WACK ()
+ MRG0 = Zero
+ MRG1 = Zero
+ MRG2 = Zero
+ MSTI = 0x80
+ WACK ()
+ Local0 = MRG2 /* \MRG2 */
+ Local0 |= One
+ MRG0 = Zero
+ MRG1 = Zero
+ MRG2 = Local0
+ MSTI = 0x81
+ WACK ()
+ }
+
+ Scope (_SB)
+ {
+ Name (PR00, Package (0x2F)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ LNKC,
+ Zero
+ }
+ })
+ Name (AR00, Package (0x2F)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ Zero,
+ 0x12
+ }
+ })
+ Name (PR12, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKB,
+ Zero
+ }
+ })
+ Name (AR12, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x11
+ }
+ })
+ Name (PR13, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKC,
+ Zero
+ }
+ })
+ Name (AR13, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x12
+ }
+ })
+ Name (PR14, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ }
+ })
+ Name (AR14, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x13
+ }
+ })
+ Name (PR15, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKA,
+ Zero
+ }
+ })
+ Name (AR15, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x10
+ }
+ })
+ Name (PR16, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKB,
+ Zero
+ }
+ })
+ Name (AR16, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x11
+ }
+ })
+ Name (PR17, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKC,
+ Zero
+ }
+ })
+ Name (AR17, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x12
+ }
+ })
+ Name (PR20, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ }
+ })
+ Name (AR20, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x13
+ }
+ })
+ Name (PR21, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKA,
+ Zero
+ }
+ })
+ Name (AR21, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x10
+ }
+ })
+ Name (PR22, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKB,
+ Zero
+ }
+ })
+ Name (AR22, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x11
+ }
+ })
+ Name (PR23, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKC,
+ Zero
+ }
+ })
+ Name (AR23, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x12
+ }
+ })
+ Name (PR0C, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ }
+ })
+ Name (AR0C, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ Zero,
+ 0x14
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ Zero,
+ 0x15
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ Zero,
+ 0x16
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ Zero,
+ 0x17
+ }
+ })
+ Name (PRSA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {4,5,7,10,11,14,15}
+ })
+ Alias (PRSA, PRSB)
+ Alias (PRSA, PRSC)
+ Alias (PRSA, PRSD)
+ Alias (PRSA, PRSE)
+ Alias (PRSA, PRSF)
+ Alias (PRSA, PRSG)
+ Alias (PRSA, PRSH)
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID
+ Name (_ADR, 0x00180000) // _ADR: Address
+ Method (^BN00, 0, NotSerialized)
+ {
+ Return (Zero)
+ }
+
+ Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number
+ {
+ Return (BN00 ())
+ }
+
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (AR00) /* \_SB_.AR00 */
+ }
+
+ Return (PR00) /* \_SB_.PR00 */
+ }
+
+ Name (CPRB, One)
+ Name (LVGA, 0x01)
+ Name (STAV, 0x0F)
+ Name (BRB, 0x0000)
+ Name (BRL, 0x0100)
+ Name (IOB, 0x1000)
+ Name (IOL, 0xF000)
+ Name (MBB, 0xC0000000)
+ Name (MBL, 0x40000000)
+ Name (MABL, 0x00000000)
+ Name (MABH, 0x00000000)
+ Name (MALL, 0x00000000)
+ Name (MALH, 0x00000000)
+ Name (MAML, 0x00000000)
+ Name (MAMH, 0x00000000)
+ Name (CRS1, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x007F, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0080, // Length
+ ,, _Y00)
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x03AF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x03B0, // Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x03E0, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0918, // Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0000, // Length
+ ,, _Y02, TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0x0FFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0300, // Length
+ ,, _Y01, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0x00000000, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00000000, // Length
+ ,, _Y03, AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000C0000, // Range Minimum
+ 0x000DFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x02000000, // Range Minimum
+ 0xFFDFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xFDFC0000, // Length
+ ,, _Y04, AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Range Minimum
+ 0x0000000000000000, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000000000000, // Length
+ ,, _Y05, AddressRangeMemory, TypeStatic)
+ })
+ Name (CRS2, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0080, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0080, // Length
+ ,, _Y06)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0000, // Length
+ ,, _Y08, TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0000, // Length
+ ,, _Y07, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0x00000000, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00000000, // Length
+ ,, _Y09, AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x80000000, // Range Minimum
+ 0xFFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x80000000, // Length
+ ,, _Y0A, AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Range Minimum
+ 0x0000000000000000, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000000000000, // Length
+ ,, _Y0B, AddressRangeMemory, TypeStatic)
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (STAV) /* \_SB_.PCI0.STAV */
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ If (CPRB)
+ {
+ CreateWordField (CRS1, \_SB.PCI0._Y00._MIN, MIN0) // _MIN: Minimum Base Address
+ CreateWordField (CRS1, \_SB.PCI0._Y00._MAX, MAX0) // _MAX: Maximum Base Address
+ CreateWordField (CRS1, \_SB.PCI0._Y00._LEN, LEN0) // _LEN: Length
+ MIN0 = BRB /* \_SB_.PCI0.BRB_ */
+ LEN0 = BRL /* \_SB_.PCI0.BRL_ */
+ Local0 = LEN0 /* \_SB_.PCI0._CRS.LEN0 */
+ MAX0 = (MIN0 + Local0--)
+ CreateWordField (CRS1, \_SB.PCI0._Y01._MIN, MIN1) // _MIN: Minimum Base Address
+ CreateWordField (CRS1, \_SB.PCI0._Y01._MAX, MAX1) // _MAX: Maximum Base Address
+ CreateWordField (CRS1, \_SB.PCI0._Y01._LEN, LEN1) // _LEN: Length
+ If ((IOB == 0x1000))
+ {
+ Local0 = IOL /* \_SB_.PCI0.IOL_ */
+ MAX1 = (IOB + Local0--)
+ Local0 = (MAX1 - MIN1) /* \_SB_.PCI0._CRS.MIN1 */
+ LEN1 = (Local0 + One)
+ }
+ Else
+ {
+ MIN1 = IOB /* \_SB_.PCI0.IOB_ */
+ LEN1 = IOL /* \_SB_.PCI0.IOL_ */
+ Local0 = LEN1 /* \_SB_.PCI0._CRS.LEN1 */
+ MAX1 = (MIN1 + Local0--)
+ }
+
+ If (((LVGA == One) || (LVGA == 0x55)))
+ {
+ If (VGAF)
+ {
+ CreateWordField (CRS1, \_SB.PCI0._Y02._MIN, IMN1) // _MIN: Minimum Base Address
+ CreateWordField (CRS1, \_SB.PCI0._Y02._MAX, IMX1) // _MAX: Maximum Base Address
+ CreateWordField (CRS1, \_SB.PCI0._Y02._LEN, ILN1) // _LEN: Length
+ IMN1 = 0x03B0
+ IMX1 = 0x03DF
+ ILN1 = 0x30
+ CreateDWordField (CRS1, \_SB.PCI0._Y03._MIN, VMN1) // _MIN: Minimum Base Address
+ CreateDWordField (CRS1, \_SB.PCI0._Y03._MAX, VMX1) // _MAX: Maximum Base Address
+ CreateDWordField (CRS1, \_SB.PCI0._Y03._LEN, VLN1) // _LEN: Length
+ VMN1 = 0x000A0000
+ VMX1 = 0x000BFFFF
+ VLN1 = 0x00020000
+ VGAF = Zero
+ }
+ }
+
+ CreateDWordField (CRS1, \_SB.PCI0._Y04._MIN, MIN3) // _MIN: Minimum Base Address
+ CreateDWordField (CRS1, \_SB.PCI0._Y04._MAX, MAX3) // _MAX: Maximum Base Address
+ CreateDWordField (CRS1, \_SB.PCI0._Y04._LEN, LEN3) // _LEN: Length
+ MIN3 = MBB /* \_SB_.PCI0.MBB_ */
+ LEN3 = MBL /* \_SB_.PCI0.MBL_ */
+ Local0 = LEN3 /* \_SB_.PCI0._CRS.LEN3 */
+ MAX3 = (MIN3 + Local0--)
+ If ((MALH || MALL))
+ {
+ CreateDWordField (CRS1, \_SB.PCI0._Y05._MIN, MN8L) // _MIN: Minimum Base Address
+ Local0 = (0xB4 + 0x04)
+ CreateDWordField (CRS1, Local0, MN8H)
+ MN8L = MABL /* \_SB_.PCI0.MABL */
+ MN8H = MABH /* \_SB_.PCI0.MABH */
+ CreateDWordField (CRS1, \_SB.PCI0._Y05._MAX, MX8L) // _MAX: Maximum Base Address
+ Local1 = (0xBC + 0x04)
+ CreateDWordField (CRS1, Local1, MX8H)
+ CreateDWordField (CRS1, \_SB.PCI0._Y05._LEN, LN8L) // _LEN: Length
+ Local2 = (0xCC + 0x04)
+ CreateDWordField (CRS1, Local2, LN8H)
+ MN8L = MABL /* \_SB_.PCI0.MABL */
+ MN8H = MABH /* \_SB_.PCI0.MABH */
+ LN8L = MALL /* \_SB_.PCI0.MALL */
+ LN8H = MALH /* \_SB_.PCI0.MALH */
+ MX8L = MAML /* \_SB_.PCI0.MAML */
+ MX8H = MAMH /* \_SB_.PCI0.MAMH */
+ }
+
+ Return (CRS1) /* \_SB_.PCI0.CRS1 */
+ }
+ Else
+ {
+ CreateWordField (CRS2, \_SB.PCI0._Y06._MIN, MIN2) // _MIN: Minimum Base Address
+ CreateWordField (CRS2, \_SB.PCI0._Y06._MAX, MAX2) // _MAX: Maximum Base Address
+ CreateWordField (CRS2, \_SB.PCI0._Y06._LEN, LEN2) // _LEN: Length
+ MIN2 = BRB /* \_SB_.PCI0.BRB_ */
+ LEN2 = BRL /* \_SB_.PCI0.BRL_ */
+ Local1 = LEN2 /* \_SB_.PCI0._CRS.LEN2 */
+ MAX2 = (MIN2 + Local1--)
+ CreateWordField (CRS2, \_SB.PCI0._Y07._MIN, MIN4) // _MIN: Minimum Base Address
+ CreateWordField (CRS2, \_SB.PCI0._Y07._MAX, MAX4) // _MAX: Maximum Base Address
+ CreateWordField (CRS2, \_SB.PCI0._Y07._LEN, LEN4) // _LEN: Length
+ MIN4 = IOB /* \_SB_.PCI0.IOB_ */
+ LEN4 = IOL /* \_SB_.PCI0.IOL_ */
+ Local1 = LEN4 /* \_SB_.PCI0._CRS.LEN4 */
+ MAX4 = (MIN4 + Local1--)
+ If (LVGA)
+ {
+ CreateWordField (CRS2, \_SB.PCI0._Y08._MIN, IMN2) // _MIN: Minimum Base Address
+ CreateWordField (CRS2, \_SB.PCI0._Y08._MAX, IMX2) // _MAX: Maximum Base Address
+ CreateWordField (CRS2, \_SB.PCI0._Y08._LEN, ILN2) // _LEN: Length
+ IMN2 = 0x03B0
+ IMX2 = 0x03DF
+ ILN2 = 0x30
+ CreateDWordField (CRS2, \_SB.PCI0._Y09._MIN, VMN2) // _MIN: Minimum Base Address
+ CreateDWordField (CRS2, \_SB.PCI0._Y09._MAX, VMX2) // _MAX: Maximum Base Address
+ CreateDWordField (CRS2, \_SB.PCI0._Y09._LEN, VLN2) // _LEN: Length
+ VMN2 = 0x000A0000
+ VMX2 = 0x000BFFFF
+ VLN2 = 0x00020000
+ }
+
+ CreateDWordField (CRS2, \_SB.PCI0._Y0A._MIN, MIN5) // _MIN: Minimum Base Address
+ CreateDWordField (CRS2, \_SB.PCI0._Y0A._MAX, MAX5) // _MAX: Maximum Base Address
+ CreateDWordField (CRS2, \_SB.PCI0._Y0A._LEN, LEN5) // _LEN: Length
+ MIN5 = MBB /* \_SB_.PCI0.MBB_ */
+ LEN5 = MBL /* \_SB_.PCI0.MBL_ */
+ Local1 = LEN5 /* \_SB_.PCI0._CRS.LEN5 */
+ MAX5 = (MIN5 + Local1--)
+ If ((MALH || MALL))
+ {
+ CreateDWordField (CRS2, \_SB.PCI0._Y0B._MIN, MN9L) // _MIN: Minimum Base Address
+ Local0 = (0x72 + 0x04)
+ CreateDWordField (CRS2, Local0, MN9H)
+ CreateDWordField (CRS2, \_SB.PCI0._Y0B._MAX, MX9L) // _MAX: Maximum Base Address
+ Local1 = (0x7A + 0x04)
+ CreateDWordField (CRS2, Local1, MX9H)
+ CreateDWordField (CRS2, \_SB.PCI0._Y0B._LEN, LN9L) // _LEN: Length
+ Local2 = (0x8A + 0x04)
+ CreateDWordField (CRS2, Local2, LN9H)
+ MN9L = MABL /* \_SB_.PCI0.MABL */
+ MN9H = MABH /* \_SB_.PCI0.MABH */
+ LN9L = MALL /* \_SB_.PCI0.MALL */
+ LN9H = MALH /* \_SB_.PCI0.MALH */
+ MX9L = MAML /* \_SB_.PCI0.MAML */
+ MX9H = MAMH /* \_SB_.PCI0.MAMH */
+ }
+
+ Return (CRS2) /* \_SB_.PCI0.CRS2 */
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (AMDN)
+ {
+ Name (_HID, EisaId ("PNP0C01") /* System Board */) // _HID: Hardware ID
+ Name (_UID, 0xC8) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (NPTR, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0x00000000, // Address Base
+ 0x00000000, // Address Length
+ _Y0C)
+ })
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateDWordField (NPTR, \_SB.PCI0.AMDN._Y0C._LEN, PL) // _LEN: Length
+ CreateDWordField (NPTR, \_SB.PCI0.AMDN._Y0C._BAS, PB) // _BAS: Base Address
+ PB = PEBS /* \PEBS */
+ PL = PEBL /* \PEBL */
+ Return (NPTR) /* \_SB_.PCI0.AMDN.NPTR */
+ }
+ }
+ }
+ }
+
+ Method (NPTS, 1, NotSerialized)
+ {
+ APTS (Arg0)
+ }
+
+ Method (NWAK, 1, NotSerialized)
+ {
+ AWAK (Arg0)
+ }
+
+ Device (GNBD)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Scope (\)
+ {
+ OperationRegion (ATFB, SystemMemory, 0xFFFFFF00, 0x0105)
+ Field (ATFB, AnyAcc, NoLock, Preserve)
+ {
+ BCMD, 8,
+ DID, 32,
+ INFO, 2048
+ }
+
+ Field (ATFB, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x05),
+ INF0, 8,
+ INF1, 8,
+ INF2, 8,
+ INF3, 8,
+ INF4, 8,
+ INF5, 8,
+ INF6, 8,
+ INF7, 8
+ }
+
+ Field (ATFB, AnyAcc, NoLock, Preserve)
+ {
+ AccessAs (ByteAcc, 0x00),
+ Offset (0x05),
+ INF, 8
+ }
+ }
+
+ OperationRegion (NBRV, PCI_Config, 0x08, One)
+ Field (NBRV, ByteAcc, NoLock, Preserve)
+ {
+ PREV, 8
+ }
+
+ OperationRegion (NBBR, PCI_Config, 0x1C, 0x08)
+ Field (NBBR, DWordAcc, NoLock, Preserve)
+ {
+ BR3L, 32,
+ BR3H, 32
+ }
+
+ OperationRegion (NBBI, PCI_Config, 0x84, 0x04)
+ Field (NBBI, DWordAcc, NoLock, Preserve)
+ {
+ PARB, 32
+ }
+
+ OperationRegion (NBMS, PCI_Config, 0x60, 0x08)
+ Field (NBMS, DWordAcc, NoLock, Preserve)
+ {
+ MIDX, 32,
+ MIDR, 32
+ }
+
+ Mutex (NBMM, 0x00)
+ Method (NBMR, 1, NotSerialized)
+ {
+ Acquire (NBMM, 0xFFFF)
+ Local0 = (Arg0 & 0x7F)
+ MIDX = Local0
+ Local0 = MIDR /* \_SB_.PCI0.GNBD.MIDR */
+ MIDX = 0x7F
+ Release (NBMM)
+ Return (Local0)
+ }
+
+ Method (NBMW, 2, NotSerialized)
+ {
+ Acquire (NBMM, 0xFFFF)
+ Local0 = (Arg0 & 0x7F)
+ Local0 |= 0x80
+ MIDX = Local0
+ MIDR = Arg1
+ MIDX = Local0 &= 0x7F
+ Release (NBMM)
+ }
+
+ OperationRegion (NBXP, PCI_Config, 0xE0, 0x08)
+ Field (NBXP, DWordAcc, NoLock, Preserve)
+ {
+ NBXI, 32,
+ NBXD, 32
+ }
+
+ Mutex (NBXM, 0x00)
+ Method (NBXR, 1, NotSerialized)
+ {
+ Acquire (NBXM, 0xFFFF)
+ NBXI = Arg0
+ Local0 = NBXD /* \_SB_.PCI0.GNBD.NBXD */
+ NBXI = Zero
+ Release (NBXM)
+ Return (Local0)
+ }
+
+ Method (NBXW, 2, NotSerialized)
+ {
+ Acquire (NBXM, 0xFFFF)
+ NBXI = Arg0
+ NBXD = Arg1
+ NBXI = Zero
+ Release (NBXM)
+ }
+
+ Method (GFXM, 0, NotSerialized)
+ {
+ Local0 = NBMR (0x08)
+ Local0 &= 0x0F
+ Return (Local0)
+ }
+
+ Method (GPPM, 0, NotSerialized)
+ {
+ Local0 = NBMR (0x67)
+ Local0 &= 0xF0
+ Return (Local0)
+ }
+
+ Method (GPPX, 0, NotSerialized)
+ {
+ Local0 = NBMR (0x2D)
+ Local0 >>= 0x07
+ Local0 &= 0x0F
+ Return (Local0)
+ }
+
+ Method (XPTR, 2, NotSerialized)
+ {
+ If (((Arg0 < 0x02) && (Arg0 > 0x07)))
+ {
+ Return (Zero)
+ }
+ Else
+ {
+ Local0 = GPPM ()
+ Local1 = GPPX ()
+ Local0 = One
+ If ((Arg0 < 0x04))
+ {
+ Local1 = (Arg0 + 0x02)
+ }
+ Else
+ {
+ Local1 = (Arg0 + 0x11)
+ }
+
+ Local0 <<= Local1
+ Local2 = NBMR (0x08)
+ If (Arg1)
+ {
+ Local2 &= ~Local0
+ }
+ Else
+ {
+ Local2 |= Local0
+ }
+
+ NBMW (0x08, Local2)
+ Return (Ones)
+ }
+ }
+
+ Name (PX3L, 0x80000000)
+ Name (PX3H, 0x80000000)
+ Name (PX3S, 0x10000000)
+ Name (PX3K, 0xF0000000)
+ Mutex (BR3X, 0x00)
+ Method (BR3M, 0, NotSerialized)
+ {
+ Local0 = PARB /* \_SB_.PCI0.GNBD.PARB */
+ Local0 >>= 0x10
+ Local0 &= 0x07
+ If (Local0)
+ {
+ Local1 = (One << Local0)
+ Local1 = (0x1000 - Local1)
+ Local1 <<= 0x14
+ PX3K = Local1
+ Local0 = (0x00100000 >> Local0)
+ PX3S = Local0
+ }
+
+ Acquire (BR3X, 0xFFFF)
+ Local0 = NBMR (Zero)
+ Local0 &= 0xFFFFFFF7
+ NBMW (Zero, Local0)
+ Local0 = BR3L /* \_SB_.PCI0.GNBD.BR3L */
+ Local0 &= PX3K /* \_SB_.PCI0.GNBD.PX3K */
+ PX3L = Local0
+ Local0 = BR3H /* \_SB_.PCI0.GNBD.BR3H */
+ Local0 &= 0xFF
+ PX3H = Local0
+ Local0 = NBMR (Zero)
+ Local0 |= 0x08
+ NBMW (Zero, Local0)
+ Release (BR3X)
+ Return (PX3L) /* \_SB_.PCI0.GNBD.PX3L */
+ }
+
+ OperationRegion (NB2, PCI_Config, Zero, 0x0100)
+ Field (NB2, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x60),
+ MI, 32,
+ MD, 32,
+ Offset (0x90),
+ TOM, 32,
+ OI, 32,
+ OD, 32,
+ Offset (0xE0),
+ LI, 32,
+ LD, 32
+ }
+
+ Device (BROD)
+ {
+ Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (UMAS, 0x30000000)
+ Name (CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadOnly,
+ 0x00000000, // Address Base
+ 0x00000000, // Address Length
+ _Y0D)
+ })
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateDWordField (CRS, \_SB.PCI0.GNBD.BROD._Y0D._BAS, BAS1) // _BAS: Base Address
+ CreateDWordField (CRS, \_SB.PCI0.GNBD.BROD._Y0D._LEN, LEN1) // _LEN: Length
+ LEN1 = UMAS /* \_SB_.PCI0.GNBD.BROD.UMAS */
+ BAS1 = (TOM - LEN1) /* \_SB_.PCI0.GNBD.BROD._CRS.LEN1 */
+ Return (CRS) /* \_SB_.PCI0.GNBD.BROD.CRS_ */
+ }
+ }
+ }
+
+ Device (IOMA)
+ {
+ Name (_ADR, 0x02) // _ADR: Address
+ OperationRegion (NBF2, PCI_Config, Zero, 0x0100)
+ Field (NBF2, AnyAcc, NoLock, Preserve)
+ {
+ DID, 32,
+ Offset (0x44),
+ MBAS, 32
+ }
+
+ Device (^UMEM)
+ {
+ Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadOnly,
+ 0x00000000, // Address Base
+ 0x00000000, // Address Length
+ _Y0E)
+ })
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateDWordField (CRS, \_SB.PCI0.UMEM._Y0E._BAS, BAS3) // _BAS: Base Address
+ CreateDWordField (CRS, \_SB.PCI0.UMEM._Y0E._LEN, LEN3) // _LEN: Length
+ If ((^^IOMA.DID != 0xFFFFFFFF))
+ {
+ LEN3 = 0x00080000
+ BAS3 = (^^IOMA.MBAS & 0xFFFFC000)
+ }
+
+ Return (CRS) /* \_SB_.PCI0.UMEM.CRS_ */
+ }
+ }
+ }
+
+ Device (IDEC)
+ {
+ Name (_ADR, 0x00140001) // _ADR: Address
+ Name (UDMT, Package (0x08)
+ {
+ 0x78,
+ 0x5A,
+ 0x3C,
+ 0x2D,
+ 0x1E,
+ 0x14,
+ 0x0F,
+ Zero
+ })
+ Name (PIOT, Package (0x06)
+ {
+ 0x0258,
+ 0x0186,
+ 0x010E,
+ 0xB4,
+ 0x78,
+ Zero
+ })
+ Name (PITR, Package (0x06)
+ {
+ 0x99,
+ 0x47,
+ 0x34,
+ 0x22,
+ 0x20,
+ 0x99
+ })
+ Name (MDMT, Package (0x04)
+ {
+ 0x01E0,
+ 0x96,
+ 0x78,
+ Zero
+ })
+ Name (MDTR, Package (0x04)
+ {
+ 0x77,
+ 0x21,
+ 0x20,
+ 0xFF
+ })
+ OperationRegion (IDE, PCI_Config, 0x40, 0x20)
+ Field (IDE, AnyAcc, NoLock, Preserve)
+ {
+ PPIT, 16,
+ SPIT, 16,
+ PMDT, 16,
+ SMDT, 16,
+ PPIC, 8,
+ SPIC, 8,
+ PPIM, 8,
+ SPIM, 8,
+ Offset (0x14),
+ PUDC, 2,
+ SUDC, 2,
+ Offset (0x16),
+ PUDM, 8,
+ SUDM, 8
+ }
+
+ Method (GETT, 1, NotSerialized)
+ {
+ Local0 = (Arg0 & 0x0F)
+ Local1 = (Arg0 >> 0x04)
+ Return ((0x1E * ((Local0 + One) + (Local1 + One)
+ )))
+ }
+
+ Method (GTM, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, Zero, PIT1)
+ CreateByteField (Arg0, One, PIT0)
+ CreateByteField (Arg0, 0x02, MDT1)
+ CreateByteField (Arg0, 0x03, MDT0)
+ CreateByteField (Arg0, 0x04, PICX)
+ CreateByteField (Arg0, 0x05, UDCX)
+ CreateByteField (Arg0, 0x06, UDMX)
+ Name (BUF, Buffer (0x14)
+ {
+ /* 0000 */ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, /* ........ */
+ /* 0008 */ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, /* ........ */
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00 /* .... */
+ })
+ CreateDWordField (BUF, Zero, PIO0)
+ CreateDWordField (BUF, 0x04, DMA0)
+ CreateDWordField (BUF, 0x08, PIO1)
+ CreateDWordField (BUF, 0x0C, DMA1)
+ CreateDWordField (BUF, 0x10, FLAG)
+ If ((PICX & One))
+ {
+ Return (BUF) /* \_SB_.PCI0.IDEC.GTM_.BUF_ */
+ }
+
+ PIO0 = GETT (PIT0)
+ PIO1 = GETT (PIT1)
+ If ((UDCX & One))
+ {
+ FLAG |= One
+ DMA0 = DerefOf (UDMT [(UDMX & 0x0F)])
+ }
+ Else
+ {
+ DMA0 = GETT (MDT0)
+ }
+
+ If ((UDCX & 0x02))
+ {
+ FLAG |= 0x04
+ DMA1 = DerefOf (UDMT [(UDMX >> 0x04)])
+ }
+ Else
+ {
+ DMA1 = GETT (MDT1)
+ }
+
+ FLAG |= 0x1A
+ Return (BUF) /* \_SB_.PCI0.IDEC.GTM_.BUF_ */
+ }
+
+ Name (PPTM, Buffer (0x14)
+ {
+ /* 0000 */ 0x78, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, /* x....... */
+ /* 0008 */ 0x78, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, /* x....... */
+ /* 0010 */ 0x1F, 0x00, 0x00, 0x00 /* .... */
+ })
+ Method (STM, 3, NotSerialized)
+ {
+ CreateDWordField (Arg0, Zero, PIO0)
+ CreateDWordField (Arg0, 0x04, DMA0)
+ CreateDWordField (Arg0, 0x08, PIO1)
+ CreateDWordField (Arg0, 0x0C, DMA1)
+ CreateDWordField (Arg0, 0x10, FLAG)
+ Name (BUF, Buffer (0x07)
+ {
+ 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00 /* ....... */
+ })
+ CreateByteField (BUF, Zero, PIT1)
+ CreateByteField (BUF, One, PIT0)
+ CreateByteField (BUF, 0x02, MDT1)
+ CreateByteField (BUF, 0x03, MDT0)
+ CreateByteField (BUF, 0x04, PIMX)
+ CreateByteField (BUF, 0x05, UDCX)
+ CreateByteField (BUF, 0x06, UDMX)
+ Local0 = Match (PIOT, MLE, PIO0, MTR, Zero, Zero)
+ Divide (Local0, 0x05, Local0)
+ Local1 = Match (PIOT, MLE, PIO1, MTR, Zero, Zero)
+ Divide (Local1, 0x05, Local1)
+ PIMX = ((Local1 << 0x04) | Local0)
+ PIT0 = DerefOf (PITR [Local0])
+ PIT1 = DerefOf (PITR [Local1])
+ If ((FLAG & One))
+ {
+ Local0 = Match (UDMT, MLE, DMA0, MTR, Zero, Zero)
+ Divide (Local0, 0x07, Local0)
+ UDMX |= Local0
+ UDCX |= One
+ }
+ ElseIf ((DMA0 != 0xFFFFFFFF))
+ {
+ Local0 = Match (MDMT, MLE, DMA0, MTR, Zero, Zero)
+ MDT0 = DerefOf (MDTR [Local0])
+ }
+
+ If ((FLAG & 0x04))
+ {
+ Local0 = Match (UDMT, MLE, DMA1, MTR, Zero, Zero)
+ Divide (Local0, 0x07, Local0)
+ UDMX |= (Local0 << 0x04)
+ UDCX |= 0x02
+ }
+ ElseIf ((DMA1 != 0xFFFFFFFF))
+ {
+ Local0 = Match (MDMT, MLE, DMA1, MTR, Zero, Zero)
+ MDT1 = DerefOf (MDTR [Local0])
+ }
+
+ Return (BUF) /* \_SB_.PCI0.IDEC.STM_.BUF_ */
+ }
+
+ Method (GTF, 2, NotSerialized)
+ {
+ CreateByteField (Arg1, Zero, MDT1)
+ CreateByteField (Arg1, One, MDT0)
+ CreateByteField (Arg1, 0x02, PIMX)
+ CreateByteField (Arg1, 0x03, UDCX)
+ CreateByteField (Arg1, 0x04, UDMX)
+ If ((Arg0 == 0xA0))
+ {
+ Local0 = (PIMX & 0x0F)
+ Local1 = MDT0 /* \_SB_.PCI0.IDEC.GTF_.MDT0 */
+ Local2 = (UDCX & One)
+ Local3 = (UDMX & 0x0F)
+ }
+ Else
+ {
+ Local0 = (PIMX >> 0x04)
+ Local1 = MDT1 /* \_SB_.PCI0.IDEC.GTF_.MDT1 */
+ Local2 = (UDCX & 0x02)
+ Local3 = (UDMX >> 0x04)
+ }
+
+ Name (BUF, Buffer (0x15)
+ {
+ /* 0000 */ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, 0x03, /* ........ */
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, 0x00, 0x00, /* ........ */
+ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0xF5 /* ..... */
+ })
+ CreateByteField (BUF, One, PMOD)
+ CreateByteField (BUF, 0x08, DMOD)
+ CreateByteField (BUF, 0x05, CMDA)
+ CreateByteField (BUF, 0x0C, CMDB)
+ CreateByteField (BUF, 0x13, CMDC)
+ CMDA = Arg0
+ CMDB = Arg0
+ CMDC = Arg0
+ PMOD = (Local0 | 0x08)
+ If (Local2)
+ {
+ DMOD = (Local3 | 0x40)
+ }
+ Else
+ {
+ Local4 = Match (MDMT, MLE, GETT (Local1), MTR, Zero, Zero)
+ If ((Local4 < 0x03))
+ {
+ DMOD = (0x20 | Local4)
+ }
+ }
+
+ Return (BUF) /* \_SB_.PCI0.IDEC.GTF_.BUF_ */
+ }
+
+ Device (PRID)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Method (_GTM, 0, NotSerialized) // _GTM: Get Timing Mode
+ {
+ Name (BUF, Buffer (0x07)
+ {
+ 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00 /* ....... */
+ })
+ CreateWordField (BUF, Zero, VPIT)
+ CreateWordField (BUF, 0x02, VMDT)
+ CreateByteField (BUF, 0x04, VPIC)
+ CreateByteField (BUF, 0x05, VUDC)
+ CreateByteField (BUF, 0x06, VUDM)
+ VPIT = PPIT /* \_SB_.PCI0.IDEC.PPIT */
+ VMDT = PMDT /* \_SB_.PCI0.IDEC.PMDT */
+ VPIC = PPIC /* \_SB_.PCI0.IDEC.PPIC */
+ VUDC = PUDC /* \_SB_.PCI0.IDEC.PUDC */
+ VUDM = PUDM /* \_SB_.PCI0.IDEC.PUDM */
+ Return (PPTM) /* \_SB_.PCI0.IDEC.PPTM */
+ }
+
+ Method (_STM, 3, NotSerialized) // _STM: Set Timing Mode
+ {
+ Name (BUF, Buffer (0x07)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* ....... */
+ })
+ CreateWordField (BUF, Zero, VPIT)
+ CreateWordField (BUF, 0x02, VMDT)
+ CreateByteField (BUF, 0x04, VPIM)
+ CreateByteField (BUF, 0x05, VUDC)
+ CreateByteField (BUF, 0x06, VUDM)
+ BUF = STM (Arg0, Arg1, Arg2)
+ PPIT = VPIT /* \_SB_.PCI0.IDEC.PRID._STM.VPIT */
+ PMDT = VMDT /* \_SB_.PCI0.IDEC.PRID._STM.VMDT */
+ PPIM = VPIM /* \_SB_.PCI0.IDEC.PRID._STM.VPIM */
+ PUDC = VUDC /* \_SB_.PCI0.IDEC.PRID._STM.VUDC */
+ PUDM = VUDM /* \_SB_.PCI0.IDEC.PRID._STM.VUDM */
+ }
+
+ Device (P_D0)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Method (_GTF, 0, NotSerialized) // _GTF: Get Task File
+ {
+ Name (BUF, Buffer (0x05)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00 /* ..... */
+ })
+ CreateWordField (BUF, Zero, VMDT)
+ CreateByteField (BUF, 0x02, VPIM)
+ CreateByteField (BUF, 0x03, VUDC)
+ CreateByteField (BUF, 0x04, VUDM)
+ VMDT = PMDT /* \_SB_.PCI0.IDEC.PMDT */
+ VPIM = PPIM /* \_SB_.PCI0.IDEC.PPIM */
+ VUDC = PUDC /* \_SB_.PCI0.IDEC.PUDC */
+ VUDM = PUDM /* \_SB_.PCI0.IDEC.PUDM */
+ Return (GTF (0xA0, BUF))
+ }
+ }
+
+ Device (P_D1)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Method (_GTF, 0, NotSerialized) // _GTF: Get Task File
+ {
+ Name (BUF, Buffer (0x05)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00 /* ..... */
+ })
+ CreateWordField (BUF, Zero, VMDT)
+ CreateByteField (BUF, 0x02, VPIM)
+ CreateByteField (BUF, 0x03, VUDC)
+ CreateByteField (BUF, 0x04, VUDM)
+ VMDT = PMDT /* \_SB_.PCI0.IDEC.PMDT */
+ VPIM = PPIM /* \_SB_.PCI0.IDEC.PPIM */
+ VUDC = PUDC /* \_SB_.PCI0.IDEC.PUDC */
+ VUDM = PUDM /* \_SB_.PCI0.IDEC.PUDM */
+ Return (GTF (0xB0, BUF))
+ }
+ }
+ }
+
+ Device (SECD)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Method (_GTM, 0, NotSerialized) // _GTM: Get Timing Mode
+ {
+ Name (BUF, Buffer (0x07)
+ {
+ 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00 /* ....... */
+ })
+ CreateWordField (BUF, Zero, VPIT)
+ CreateWordField (BUF, 0x02, VMDT)
+ CreateByteField (BUF, 0x04, VPIC)
+ CreateByteField (BUF, 0x05, VUDC)
+ CreateByteField (BUF, 0x06, VUDM)
+ VPIT = SPIT /* \_SB_.PCI0.IDEC.SPIT */
+ VMDT = SMDT /* \_SB_.PCI0.IDEC.SMDT */
+ VPIC = SPIC /* \_SB_.PCI0.IDEC.SPIC */
+ VUDC = SUDC /* \_SB_.PCI0.IDEC.SUDC */
+ VUDM = SUDM /* \_SB_.PCI0.IDEC.SUDM */
+ Return (PPTM) /* \_SB_.PCI0.IDEC.PPTM */
+ }
+
+ Method (_STM, 3, NotSerialized) // _STM: Set Timing Mode
+ {
+ Name (BUF, Buffer (0x07)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* ....... */
+ })
+ CreateWordField (BUF, Zero, VPIT)
+ CreateWordField (BUF, 0x02, VMDT)
+ CreateByteField (BUF, 0x04, VPIM)
+ CreateByteField (BUF, 0x05, VUDC)
+ CreateByteField (BUF, 0x06, VUDM)
+ BUF = STM (Arg0, Arg1, Arg2)
+ SPIT = VPIT /* \_SB_.PCI0.IDEC.SECD._STM.VPIT */
+ SMDT = VMDT /* \_SB_.PCI0.IDEC.SECD._STM.VMDT */
+ SPIM = VPIM /* \_SB_.PCI0.IDEC.SECD._STM.VPIM */
+ SUDC = VUDC /* \_SB_.PCI0.IDEC.SECD._STM.VUDC */
+ SUDM = VUDM /* \_SB_.PCI0.IDEC.SECD._STM.VUDM */
+ }
+
+ Device (S_D0)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Method (_GTF, 0, NotSerialized) // _GTF: Get Task File
+ {
+ Name (BUF, Buffer (0x05)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00 /* ..... */
+ })
+ CreateWordField (BUF, Zero, VMDT)
+ CreateByteField (BUF, 0x02, VPIM)
+ CreateByteField (BUF, 0x03, VUDC)
+ CreateByteField (BUF, 0x04, VUDM)
+ VMDT = SMDT /* \_SB_.PCI0.IDEC.SMDT */
+ VPIM = SPIM /* \_SB_.PCI0.IDEC.SPIM */
+ VUDC = SUDC /* \_SB_.PCI0.IDEC.SUDC */
+ VUDM = SUDM /* \_SB_.PCI0.IDEC.SUDM */
+ Return (GTF (0xA0, BUF))
+ }
+ }
+
+ Device (S_D1)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Method (_GTF, 0, NotSerialized) // _GTF: Get Task File
+ {
+ Name (BUF, Buffer (0x05)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00 /* ..... */
+ })
+ CreateWordField (BUF, Zero, VMDT)
+ CreateByteField (BUF, 0x02, VPIM)
+ CreateByteField (BUF, 0x03, VUDC)
+ CreateByteField (BUF, 0x04, VUDM)
+ VMDT = SMDT /* \_SB_.PCI0.IDEC.SMDT */
+ VPIM = SPIM /* \_SB_.PCI0.IDEC.SPIM */
+ VUDC = SUDC /* \_SB_.PCI0.IDEC.SUDC */
+ VUDM = SUDM /* \_SB_.PCI0.IDEC.SUDM */
+ Return (GTF (0xB0, BUF))
+ }
+ }
+ }
+ }
+
+ Device (SBAZ)
+ {
+ Name (_ADR, 0x00140002) // _ADR: Address
+ OperationRegion (PCI, PCI_Config, Zero, 0x0100)
+ Field (PCI, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x42),
+ DNSP, 1,
+ DNSO, 1,
+ ENSR, 1
+ }
+
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x1B, 0x04))
+ }
+ }
+
+ Device (SBRG)
+ {
+ Name (_ADR, 0x00140003) // _ADR: Address
+ OperationRegion (RMBS, PCI_Config, Zero, 0x0100)
+ Field (RMBS, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x6C),
+ LR2S, 16,
+ LR2E, 16
+ }
+
+ Method (SPTS, 1, NotSerialized)
+ {
+ }
+
+ Method (SWAK, 1, NotSerialized)
+ {
+ If (PICM)
+ {
+ IRQC ()
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Name (SLPS, Zero)
+ }
+
+ OperationRegion (SMI0, SystemIO, SMIO, One)
+ Field (SMI0, ByteAcc, NoLock, Preserve)
+ {
+ SMIC, 8
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (S900)
+ {
+ Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_UID, 0x0700) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (CRS, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0010, // Range Minimum
+ 0x0010, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IO (Decode16,
+ 0x0022, // Range Minimum
+ 0x0022, // Range Maximum
+ 0x00, // Alignment
+ 0x1E, // Length
+ )
+ IO (Decode16,
+ 0x0063, // Range Minimum
+ 0x0063, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0065, // Range Minimum
+ 0x0065, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0067, // Range Minimum
+ 0x0067, // Range Maximum
+ 0x00, // Alignment
+ 0x09, // Length
+ )
+ IO (Decode16,
+ 0x0072, // Range Minimum
+ 0x0072, // Range Maximum
+ 0x00, // Alignment
+ 0x0E, // Length
+ )
+ IO (Decode16,
+ 0x0080, // Range Minimum
+ 0x0080, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0084, // Range Minimum
+ 0x0084, // Range Maximum
+ 0x00, // Alignment
+ 0x03, // Length
+ )
+ IO (Decode16,
+ 0x0088, // Range Minimum
+ 0x0088, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x008C, // Range Minimum
+ 0x008C, // Range Maximum
+ 0x00, // Alignment
+ 0x03, // Length
+ )
+ IO (Decode16,
+ 0x0090, // Range Minimum
+ 0x0090, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IO (Decode16,
+ 0x00A2, // Range Minimum
+ 0x00A2, // Range Maximum
+ 0x00, // Alignment
+ 0x1E, // Length
+ )
+ IO (Decode16,
+ 0x00B1, // Range Minimum
+ 0x00B1, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x00E0, // Range Minimum
+ 0x00E0, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IO (Decode16,
+ 0x04D0, // Range Minimum
+ 0x04D0, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x040B, // Range Minimum
+ 0x040B, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x04D6, // Range Minimum
+ 0x04D6, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0C00, // Range Minimum
+ 0x0C00, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0C14, // Range Minimum
+ 0x0C14, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0C50, // Range Minimum
+ 0x0C50, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0C52, // Range Minimum
+ 0x0C52, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0C6C, // Range Minimum
+ 0x0C6C, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0C6F, // Range Minimum
+ 0x0C6F, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0CD0, // Range Minimum
+ 0x0CD0, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0CD2, // Range Minimum
+ 0x0CD2, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0CD4, // Range Minimum
+ 0x0CD4, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0CD6, // Range Minimum
+ 0x0CD6, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0CD8, // Range Minimum
+ 0x0CD8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x00, // Alignment
+ 0x00, // Length
+ _Y0F)
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x00, // Alignment
+ 0x00, // Length
+ _Y12)
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x00, // Alignment
+ 0x00, // Length
+ _Y11)
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x00, // Alignment
+ 0x00, // Length
+ _Y10)
+ IO (Decode16,
+ 0x0900, // Range Minimum
+ 0x0900, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IO (Decode16,
+ 0x0910, // Range Minimum
+ 0x0910, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IO (Decode16,
+ 0xFE00, // Range Minimum
+ 0xFE00, // Range Maximum
+ 0x00, // Alignment
+ 0xFF, // Length
+ )
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x00, // Alignment
+ 0x00, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x00, // Alignment
+ 0x00, // Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0x00000000, // Address Base
+ 0x00000000, // Address Length
+ _Y13)
+ Memory32Fixed (ReadWrite,
+ 0xFEE00000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xFED80000, // Address Base
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xFED61000, // Address Base
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0x00000000, // Address Base
+ 0x00000000, // Address Length
+ _Y14)
+ Memory32Fixed (ReadWrite,
+ 0x00000000, // Address Base
+ 0x00000000, // Address Length
+ _Y15)
+ Memory32Fixed (ReadWrite,
+ 0x00000000, // Address Base
+ 0x00000000, // Address Length
+ _Y16)
+ })
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateWordField (CRS, \_SB.PCI0.S900._Y0F._MIN, PBB) // _MIN: Minimum Base Address
+ CreateWordField (CRS, \_SB.PCI0.S900._Y0F._MAX, PBH) // _MAX: Maximum Base Address
+ CreateByteField (CRS, \_SB.PCI0.S900._Y0F._LEN, PML) // _LEN: Length
+ PBB = PMBS /* \PMBS */
+ PBH = PMBS /* \PMBS */
+ PML = PMLN /* \PMLN */
+ If (SMBB)
+ {
+ CreateWordField (CRS, \_SB.PCI0.S900._Y10._MIN, SMB1) // _MIN: Minimum Base Address
+ CreateWordField (CRS, \_SB.PCI0.S900._Y10._MAX, SMH1) // _MAX: Maximum Base Address
+ CreateByteField (CRS, \_SB.PCI0.S900._Y10._LEN, SML1) // _LEN: Length
+ SMB1 = SMBB /* \SMBB */
+ SMH1 = SMBB /* \SMBB */
+ SML1 = SMBL /* \SMBL */
+ CreateWordField (CRS, \_SB.PCI0.S900._Y11._MIN, SMB0) // _MIN: Minimum Base Address
+ CreateWordField (CRS, \_SB.PCI0.S900._Y11._MAX, SMH0) // _MAX: Maximum Base Address
+ CreateByteField (CRS, \_SB.PCI0.S900._Y11._LEN, SML0) // _LEN: Length
+ SMB0 = SMB0 /* \_SB_.PCI0.S900._CRS.SMB0 */
+ SMH0 = SMB0 /* \_SB_.PCI0.S900._CRS.SMB0 */
+ SML0 = SMBM /* \SMBM */
+ }
+
+ If (GPBS)
+ {
+ CreateWordField (CRS, \_SB.PCI0.S900._Y12._MIN, IGB) // _MIN: Minimum Base Address
+ CreateWordField (CRS, \_SB.PCI0.S900._Y12._MAX, IGH) // _MAX: Maximum Base Address
+ CreateByteField (CRS, \_SB.PCI0.S900._Y12._LEN, IGL) // _LEN: Length
+ IGB = GPBS /* \GPBS */
+ IGH = GPBS /* \GPBS */
+ IGL = GPLN /* \GPLN */
+ }
+
+ If (APCB)
+ {
+ CreateDWordField (CRS, \_SB.PCI0.S900._Y13._BAS, APB) // _BAS: Base Address
+ CreateDWordField (CRS, \_SB.PCI0.S900._Y13._LEN, APL) // _LEN: Length
+ APB = APCB /* \APCB */
+ APL = APCL /* \APCL */
+ }
+
+ If (SPIB)
+ {
+ CreateDWordField (CRS, \_SB.PCI0.S900._Y14._BAS, SPIB) // _BAS: Base Address
+ CreateDWordField (CRS, \_SB.PCI0.S900._Y14._LEN, SPIL) // _LEN: Length
+ SPIB = \SPIB
+ SPIL = \SPIL
+ }
+
+ If (HPTB)
+ {
+ CreateDWordField (CRS, \_SB.PCI0.S900._Y15._BAS, HXTB) // _BAS: Base Address
+ CreateDWordField (CRS, \_SB.PCI0.S900._Y15._LEN, HXTL) // _LEN: Length
+ HXTB = HPTB /* \HPTB */
+ HXTL = HPTL /* \HPTL */
+ }
+
+ CreateDWordField (CRS, \_SB.PCI0.S900._Y16._BAS, ROMB) // _BAS: Base Address
+ CreateDWordField (CRS, \_SB.PCI0.S900._Y16._LEN, ROML) // _LEN: Length
+ If (^^SBRG.LR2S)
+ {
+ ROMB = (^^SBRG.LR2S << 0x10)
+ ROML = (((^^SBRG.LR2E - ^^SBRG.LR2S) + One) << 0x10)
+ }
+ Else
+ {
+ ROMB = ROMS /* \ROMS */
+ ROML = (Zero - ROMS) /* \ROMS */
+ }
+
+ Return (CRS) /* \_SB_.PCI0.S900.CRS_ */
+ }
+ }
+ }
+ }
+
+ Device (SIO1)
+ {
+ Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_UID, 0x0111) // _UID: Unique ID
+ Name (CRS, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x00, // Alignment
+ 0x00, // Length
+ _Y17)
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x00, // Alignment
+ 0x00, // Length
+ _Y18)
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x00, // Alignment
+ 0x00, // Length
+ _Y19)
+ })
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ If (((SP1O < 0x03F0) && (SP1O > 0xF0)))
+ {
+ CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y17._MIN, GPI0) // _MIN: Minimum Base Address
+ CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y17._MAX, GPI1) // _MAX: Maximum Base Address
+ CreateByteField (CRS, \_SB.PCI0.SBRG.SIO1._Y17._LEN, GPIL) // _LEN: Length
+ GPI0 = SP1O /* \SP1O */
+ GPI1 = SP1O /* \SP1O */
+ GPIL = 0x02
+ }
+
+ If (IO1B)
+ {
+ CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y18._MIN, GP10) // _MIN: Minimum Base Address
+ CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y18._MAX, GP11) // _MAX: Maximum Base Address
+ CreateByteField (CRS, \_SB.PCI0.SBRG.SIO1._Y18._LEN, GPL1) // _LEN: Length
+ GP10 = IO1B /* \IO1B */
+ GP11 = IO1B /* \IO1B */
+ GPL1 = IO1L /* \IO1L */
+ }
+
+ If (IO2B)
+ {
+ CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y19._MIN, GP20) // _MIN: Minimum Base Address
+ CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y19._MAX, GP21) // _MAX: Maximum Base Address
+ CreateByteField (CRS, \_SB.PCI0.SBRG.SIO1._Y19._LEN, GPL2) // _LEN: Length
+ GP20 = IO2B /* \IO2B */
+ GP21 = IO2B /* \IO2B */
+ GPL2 = IO2L /* \IO2L */
+ }
+
+ Return (CRS) /* \_SB_.PCI0.SBRG.SIO1.CRS_ */
+ }
+
+ Name (DCAT, Package (0x10)
+ {
+ One,
+ 0x02,
+ 0x03,
+ Zero,
+ 0xFF,
+ 0xFF,
+ 0xFF,
+ 0xFF,
+ 0xFF,
+ 0xFF,
+ 0x05,
+ 0xFF,
+ 0xFF,
+ 0xFF,
+ 0x05,
+ 0xFF
+ })
+ Mutex (MUT0, 0x00)
+ Method (ENFG, 1, NotSerialized)
+ {
+ Acquire (MUT0, 0x0FFF)
+ INDX = 0x87
+ INDX = 0x87
+ LDN = Arg0
+ }
+
+ Method (EXFG, 0, NotSerialized)
+ {
+ INDX = 0xAA
+ Release (MUT0)
+ }
+
+ Method (LPTM, 1, NotSerialized)
+ {
+ ENFG (CGLD (Arg0))
+ Local0 = (OPT0 & 0x02)
+ EXFG ()
+ Return (Local0)
+ }
+
+ Method (UHID, 1, NotSerialized)
+ {
+ ENFG (CGLD (Arg0))
+ Local0 = (OPT1 & 0x10)
+ EXFG ()
+ If (Local0)
+ {
+ Return (0x1005D041)
+ }
+ Else
+ {
+ Return (0x0105D041)
+ }
+ }
+
+ OperationRegion (IOID, SystemIO, SP1O, 0x02)
+ Field (IOID, ByteAcc, NoLock, Preserve)
+ {
+ INDX, 8,
+ DATA, 8
+ }
+
+ IndexField (INDX, DATA, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ LDN, 8,
+ Offset (0x26),
+ INTT, 8,
+ CR27, 8,
+ CR28, 8,
+ CR29, 8,
+ CR2A, 8,
+ CR2B, 8,
+ Offset (0x2D),
+ CR2D, 8,
+ Offset (0x30),
+ ACTR, 8,
+ Offset (0x60),
+ IOAH, 8,
+ IOAL, 8,
+ IOH2, 8,
+ IOL2, 8,
+ Offset (0x70),
+ INTR, 4,
+ REVS, 4,
+ Offset (0x74),
+ DMCH, 8,
+ Offset (0xE0),
+ RGE0, 8,
+ RGE1, 8,
+ RGE2, 8,
+ RGE3, 8,
+ RGE4, 8,
+ RGE5, 8,
+ RGE6, 8,
+ RGE7, 8,
+ RGE8, 8,
+ RGE9, 8,
+ Offset (0xF0),
+ OPT0, 8,
+ OPT1, 8,
+ OPT2, 8,
+ OPT3, 8,
+ OPT4, 8,
+ OPT5, 8,
+ OPT6, 8,
+ OPT7, 8,
+ OPT8, 8,
+ OPT9, 8
+ }
+
+ Method (CGLD, 1, NotSerialized)
+ {
+ Return (DerefOf (DCAT [Arg0]))
+ }
+
+ Method (DSTA, 1, NotSerialized)
+ {
+ ENFG (CGLD (Arg0))
+ Local0 = ACTR /* \_SB_.PCI0.SBRG.SIO1.ACTR */
+ If ((Local0 == 0xFF))
+ {
+ Return (Zero)
+ }
+
+ Local0 &= One
+ If ((Arg0 < 0x10))
+ {
+ IOST |= (Local0 << Arg0)
+ }
+
+ If (Local0)
+ {
+ Return (0x0F)
+ }
+ ElseIf ((Arg0 < 0x10))
+ {
+ If (((One << Arg0) & IOST))
+ {
+ Return (0x0D)
+ }
+ Else
+ {
+ Return (Zero)
+ }
+ }
+ Else
+ {
+ Local0 = ((IOAH << 0x08) | IOAL) /* \_SB_.PCI0.SBRG.SIO1.IOAL */
+ If (Local0)
+ {
+ Return (0x0D)
+ }
+
+ Return (Zero)
+ }
+
+ EXFG ()
+ }
+
+ Method (DCNT, 2, NotSerialized)
+ {
+ ENFG (CGLD (Arg0))
+ If (((DMCH < 0x04) && ((Local1 = (DMCH & 0x03)) != Zero)))
+ {
+ RDMA (Arg0, Arg1, Local1++)
+ }
+
+ ACTR = Arg1
+ Local1 = (IOAH << 0x08)
+ Local1 |= IOAL
+ RRIO (Arg0, Arg1, Local1, 0x08)
+ EXFG ()
+ }
+
+ Name (CRS1, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x01, // Alignment
+ 0x00, // Length
+ _Y1C)
+ IRQNoFlags (_Y1A)
+ {}
+ DMA (Compatibility, NotBusMaster, Transfer8, _Y1B)
+ {}
+ })
+ CreateWordField (CRS1, \_SB.PCI0.SBRG.SIO1._Y1A._INT, IRQM) // _INT: Interrupts
+ CreateByteField (CRS1, \_SB.PCI0.SBRG.SIO1._Y1B._DMA, DMAM) // _DMA: Direct Memory Access
+ CreateWordField (CRS1, \_SB.PCI0.SBRG.SIO1._Y1C._MIN, IO11) // _MIN: Minimum Base Address
+ CreateWordField (CRS1, \_SB.PCI0.SBRG.SIO1._Y1C._MAX, IO12) // _MAX: Maximum Base Address
+ CreateByteField (CRS1, \_SB.PCI0.SBRG.SIO1._Y1C._LEN, LEN1) // _LEN: Length
+ Name (CRS2, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x01, // Alignment
+ 0x00, // Length
+ _Y1F)
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x01, // Alignment
+ 0x00, // Length
+ _Y20)
+ IRQNoFlags (_Y1D)
+ {}
+ DMA (Compatibility, NotBusMaster, Transfer8, _Y1E)
+ {}
+ })
+ CreateWordField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1D._INT, IRQE) // _INT: Interrupts
+ CreateByteField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1E._DMA, DMAE) // _DMA: Direct Memory Access
+ CreateWordField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1F._MIN, IO21) // _MIN: Minimum Base Address
+ CreateWordField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1F._MAX, IO22) // _MAX: Maximum Base Address
+ CreateByteField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1F._LEN, LEN2) // _LEN: Length
+ CreateWordField (CRS2, \_SB.PCI0.SBRG.SIO1._Y20._MIN, IO31) // _MIN: Minimum Base Address
+ CreateWordField (CRS2, \_SB.PCI0.SBRG.SIO1._Y20._MAX, IO32) // _MAX: Maximum Base Address
+ CreateByteField (CRS2, \_SB.PCI0.SBRG.SIO1._Y20._LEN, LEN3) // _LEN: Length
+ Name (CRS3, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x01, // Alignment
+ 0x00, // Length
+ _Y23)
+ IRQ (Level, ActiveLow, Shared, _Y21)
+ {}
+ DMA (Compatibility, NotBusMaster, Transfer8, _Y22)
+ {}
+ })
+ CreateWordField (CRS3, \_SB.PCI0.SBRG.SIO1._Y21._INT, IRQT) // _INT: Interrupts
+ CreateByteField (CRS3, \_SB.PCI0.SBRG.SIO1._Y21._HE, IRQS) // _HE_: High-Edge
+ CreateByteField (CRS3, \_SB.PCI0.SBRG.SIO1._Y22._DMA, DMAT) // _DMA: Direct Memory Access
+ CreateWordField (CRS3, \_SB.PCI0.SBRG.SIO1._Y23._MIN, IO41) // _MIN: Minimum Base Address
+ CreateWordField (CRS3, \_SB.PCI0.SBRG.SIO1._Y23._MAX, IO42) // _MAX: Maximum Base Address
+ CreateByteField (CRS3, \_SB.PCI0.SBRG.SIO1._Y23._LEN, LEN4) // _LEN: Length
+ Method (DCRS, 2, NotSerialized)
+ {
+ ENFG (CGLD (Arg0))
+ IO11 = (IOAH << 0x08)
+ IO11 |= IOAL /* \_SB_.PCI0.SBRG.SIO1.IO11 */
+ IO12 = IO11 /* \_SB_.PCI0.SBRG.SIO1.IO11 */
+ LEN1 = 0x08
+ If (INTR)
+ {
+ IRQM = (One << INTR) /* \_SB_.PCI0.SBRG.SIO1.INTR */
+ }
+ Else
+ {
+ IRQM = Zero
+ }
+
+ If (((DMCH > 0x03) || (Arg1 == Zero)))
+ {
+ DMAM = Zero
+ }
+ Else
+ {
+ Local1 = (DMCH & 0x03)
+ DMAM = (One << Local1)
+ }
+
+ EXFG ()
+ Return (CRS1) /* \_SB_.PCI0.SBRG.SIO1.CRS1 */
+ }
+
+ Method (DCR2, 2, NotSerialized)
+ {
+ ENFG (CGLD (Arg0))
+ IO21 = (IOAH << 0x08)
+ IO21 |= IOAL /* \_SB_.PCI0.SBRG.SIO1.IO21 */
+ IO22 = IO21 /* \_SB_.PCI0.SBRG.SIO1.IO21 */
+ LEN2 = 0x08
+ IO31 = (IOH2 << 0x08)
+ IO31 |= IOL2 /* \_SB_.PCI0.SBRG.SIO1.IO31 */
+ IO32 = IO31 /* \_SB_.PCI0.SBRG.SIO1.IO31 */
+ LEN3 = 0x08
+ If (INTR)
+ {
+ IRQE = (One << INTR) /* \_SB_.PCI0.SBRG.SIO1.INTR */
+ }
+ Else
+ {
+ IRQE = Zero
+ }
+
+ If (((DMCH > 0x03) || (Arg1 == Zero)))
+ {
+ DMAE = Zero
+ }
+ Else
+ {
+ Local1 = (DMCH & 0x03)
+ DMAE = (One << Local1)
+ }
+
+ EXFG ()
+ Return (CRS2) /* \_SB_.PCI0.SBRG.SIO1.CRS2 */
+ }
+
+ Method (DCR3, 2, NotSerialized)
+ {
+ ENFG (CGLD (Arg0))
+ IO41 = (IOAH << 0x08)
+ IO41 |= IOAL /* \_SB_.PCI0.SBRG.SIO1.IO41 */
+ IO42 = IO41 /* \_SB_.PCI0.SBRG.SIO1.IO41 */
+ LEN4 = 0x08
+ If (INTR)
+ {
+ IRQT = (One << INTR) /* \_SB_.PCI0.SBRG.SIO1.INTR */
+ If ((INTT & One))
+ {
+ If ((INTT & 0x02))
+ {
+ IRQS = 0x19
+ }
+ Else
+ {
+ IRQS = 0x18
+ }
+ }
+ Else
+ {
+ IRQS = Zero
+ }
+ }
+ Else
+ {
+ IRQT = Zero
+ }
+
+ If (((DMCH > 0x03) || (Arg1 == Zero)))
+ {
+ DMAT = Zero
+ }
+ Else
+ {
+ Local1 = (DMCH & 0x03)
+ DMAT = (One << Local1)
+ }
+
+ EXFG ()
+ Return (CRS3) /* \_SB_.PCI0.SBRG.SIO1.CRS3 */
+ }
+
+ Method (DSRS, 2, NotSerialized)
+ {
+ If (((Arg1 == 0x02) & LPTM (Arg1)))
+ {
+ DSR2 (Arg0, Arg1)
+ }
+ Else
+ {
+ CreateWordField (Arg0, 0x09, IRQM)
+ CreateByteField (Arg0, 0x0C, DMAM)
+ CreateWordField (Arg0, 0x02, IO11)
+ ENFG (CGLD (Arg1))
+ IOAL = (IO11 & 0xFF)
+ IOAH = (IO11 >> 0x08)
+ If (IRQM)
+ {
+ FindSetRightBit (IRQM, Local0)
+ INTR = (Local0 - One)
+ }
+ Else
+ {
+ INTR = Zero
+ }
+
+ If (DMAM)
+ {
+ FindSetRightBit (DMAM, Local0)
+ DMCH = (Local0 - One)
+ }
+ Else
+ {
+ DMCH = 0x04
+ }
+
+ EXFG ()
+ DCNT (Arg1, One)
+ Local2 = Arg1
+ If ((Local2 > Zero))
+ {
+ Local2 -= One
+ }
+ }
+ }
+
+ Method (DSR2, 2, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x11, IRQE)
+ CreateByteField (Arg0, 0x14, DMAE)
+ CreateWordField (Arg0, 0x02, IO21)
+ CreateWordField (Arg0, 0x0A, IO31)
+ ENFG (CGLD (Arg1))
+ IOAL = (IO21 & 0xFF)
+ IOAH = (IO21 >> 0x08)
+ IOL2 = (IO31 & 0xFF)
+ IOH2 = (IO31 >> 0x08)
+ If (IRQE)
+ {
+ FindSetRightBit (IRQE, Local0)
+ INTR = (Local0 - One)
+ }
+ Else
+ {
+ INTR = Zero
+ }
+
+ If (DMAE)
+ {
+ FindSetRightBit (DMAE, Local0)
+ DMCH = (Local0 - One)
+ }
+ Else
+ {
+ DMCH = 0x04
+ }
+
+ EXFG ()
+ DCNT (Arg1, One)
+ Local2 = Arg1
+ If ((Local2 > Zero))
+ {
+ Local2 -= One
+ }
+ }
+
+ Method (DSR3, 2, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x02, IO41)
+ CreateWordField (Arg0, 0x09, IRQT)
+ CreateByteField (Arg0, 0x0B, IRQS)
+ CreateByteField (Arg0, 0x0D, DMAT)
+ ENFG (CGLD (Arg1))
+ IOAL = (IO41 & 0xFF)
+ IOAH = (IO41 >> 0x08)
+ If (IRQT)
+ {
+ FindSetRightBit (IRQT, Local0)
+ INTR = (Local0 - One)
+ If ((IRQS & 0x10))
+ {
+ If ((IRQS & One))
+ {
+ INTT |= 0x03
+ }
+ Else
+ {
+ Local0 = (INTT & 0xFC)
+ INTT = (Local0 | One)
+ }
+ }
+ }
+ Else
+ {
+ INTR = Zero
+ }
+
+ If (DMAT)
+ {
+ FindSetRightBit (DMAT, Local0)
+ DMCH = (Local0 - One)
+ }
+ Else
+ {
+ DMCH = 0x04
+ }
+
+ EXFG ()
+ DCNT (Arg1, One)
+ Local2 = Arg1
+ If ((Local2 > Zero))
+ {
+ Local2 -= One
+ }
+ }
+ }
+
+ Name (PMFG, Zero)
+ Method (SIOS, 1, NotSerialized)
+ {
+ If ((0x05 != Arg0))
+ {
+ ^SIO1.ENFG (0x0A)
+ If (KBFG)
+ {
+ ^SIO1.OPT0 |= 0x20
+ }
+ Else
+ {
+ ^SIO1.OPT0 &= 0xDF
+ }
+
+ If (MSFG)
+ {
+ ^SIO1.OPT0 |= 0x40
+ }
+ Else
+ {
+ ^SIO1.OPT0 &= 0xBF
+ }
+
+ ^SIO1.OPT1 = 0xFF
+ ^SIO1.EXFG ()
+ }
+ }
+
+ Method (SIOW, 1, NotSerialized)
+ {
+ ^SIO1.ENFG (0x0A)
+ PMFG = ^SIO1.OPT1 /* \_SB_.PCI0.SBRG.SIO1.OPT1 */
+ ^SIO1.OPT1 = 0xFF
+ ^SIO1.OPT0 &= 0x9F
+ ^SIO1.EXFG ()
+ }
+
+ Method (SIOH, 0, NotSerialized)
+ {
+ If ((PMFG & 0x20))
+ {
+ Notify (PS2K, 0x02) // Device Wake
+ }
+
+ If ((PMFG & 0x40))
+ {
+ Notify (PS2M, 0x02) // Device Wake
+ }
+ }
+
+ Device (PS2K)
+ {
+ Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+ {
+ Return (HIDK) /* \HIDK */
+ }
+
+ Method (_CID, 0, NotSerialized) // _CID: Compatible ID
+ {
+ Return (CIDK) /* \CIDK */
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((IOST & 0x0400))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (Zero)
+ }
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ }
+ EndDependentFn ()
+ })
+ Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake
+ {
+ KBFG = Arg0
+ }
+ }
+
+ Scope (\)
+ {
+ Name (KBFG, One)
+ }
+
+ Method (PS2K._PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x1D, 0x03))
+ }
+
+ Device (PS2M)
+ {
+ Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+ {
+ Return (HIDM) /* \HIDM */
+ }
+
+ Method (_CID, 0, NotSerialized) // _CID: Compatible ID
+ {
+ Return (CIDM) /* \CIDM */
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((IOST & 0x4000))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (Zero)
+ }
+ }
+
+ Name (CRS1, ResourceTemplate ()
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ Name (CRS2, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {12}
+ })
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ If ((IOST & 0x0400))
+ {
+ Return (CRS1) /* \_SB_.PCI0.SBRG.PS2M.CRS1 */
+ }
+ Else
+ {
+ Return (CRS2) /* \_SB_.PCI0.SBRG.PS2M.CRS2 */
+ }
+ }
+
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ IRQNoFlags ()
+ {12}
+ }
+ EndDependentFn ()
+ })
+ Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake
+ {
+ MSFG = Arg0
+ }
+ }
+
+ Scope (\)
+ {
+ Name (MSFG, One)
+ }
+
+ Method (PS2M._PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x1D, 0x03))
+ }
+
+ Device (UAR1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (^^SIO1.DSTA (Zero))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ ^^SIO1.DCNT (Zero, Zero)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (^^SIO1.DCRS (Zero, Zero))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ ^^SIO1.DSRS (Arg0, Zero)
+ }
+
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {3,4,5,6,7,10,11,12}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x02F8, // Range Minimum
+ 0x02F8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {3,4,5,6,7,10,11,12}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x03E8, // Range Minimum
+ 0x03E8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {3,4,5,6,7,10,11,12}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x02E8, // Range Minimum
+ 0x02E8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {3,4,5,6,7,10,11,12}
+ }
+ EndDependentFn ()
+ })
+ }
+
+ Device (LPTE)
+ {
+ Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+ {
+ If (^^SIO1.LPTM (0x02))
+ {
+ Return (0x0104D041)
+ }
+ Else
+ {
+ Return (0x0004D041)
+ }
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (^^SIO1.DSTA (0x02))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ ^^SIO1.DCNT (0x02, Zero)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ ^^SIO1.DCRS (0x02, One)
+ If ((^^SIO1.IO11 & 0x04))
+ {
+ ^^SIO1.LEN1 = 0x04
+ }
+
+ If (^^SIO1.LPTM (0x02))
+ {
+ ^^SIO1.IRQE = ^^SIO1.IRQM /* \_SB_.PCI0.SBRG.SIO1.IRQM */
+ ^^SIO1.DMAE = ^^SIO1.DMAM /* \_SB_.PCI0.SBRG.SIO1.DMAM */
+ ^^SIO1.IO21 = ^^SIO1.IO11 /* \_SB_.PCI0.SBRG.SIO1.IO11 */
+ ^^SIO1.IO22 = ^^SIO1.IO12 /* \_SB_.PCI0.SBRG.SIO1.IO12 */
+ ^^SIO1.LEN2 = ^^SIO1.LEN1 /* \_SB_.PCI0.SBRG.SIO1.LEN1 */
+ ^^SIO1.IO31 = (^^SIO1.IO21 + 0x0400)
+ ^^SIO1.IO32 = ^^SIO1.IO31 /* \_SB_.PCI0.SBRG.SIO1.IO31 */
+ ^^SIO1.LEN3 = ^^SIO1.LEN2 /* \_SB_.PCI0.SBRG.SIO1.LEN2 */
+ Return (^^SIO1.CRS2) /* \_SB_.PCI0.SBRG.SIO1.CRS2 */
+ }
+ Else
+ {
+ Return (^^SIO1.CRS1) /* \_SB_.PCI0.SBRG.SIO1.CRS1 */
+ }
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ ^^SIO1.DSRS (Arg0, 0x02)
+ }
+
+ Method (_PRS, 0, NotSerialized) // _PRS: Possible Resource Settings
+ {
+ If (^^SIO1.LPTM (0x02))
+ {
+ Return (EPPR) /* \_SB_.PCI0.SBRG.LPTE.EPPR */
+ }
+ Else
+ {
+ Return (LPPR) /* \_SB_.PCI0.SBRG.LPTE.LPPR */
+ }
+ }
+
+ Name (LPPR, ResourceTemplate ()
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {5}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {5,6,7,10,11,12}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x0278, // Range Minimum
+ 0x0278, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {5,6,7,10,11,12}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x03BC, // Range Minimum
+ 0x03BC, // Range Maximum
+ 0x01, // Alignment
+ 0x04, // Length
+ )
+ IRQNoFlags ()
+ {5,6,7,10,11,12}
+ }
+ EndDependentFn ()
+ })
+ Name (EPPR, ResourceTemplate ()
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IO (Decode16,
+ 0x0778, // Range Minimum
+ 0x0778, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {5}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {3}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IO (Decode16,
+ 0x0778, // Range Minimum
+ 0x0778, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {5,6,7,10,11,12}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {1,3}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x0278, // Range Minimum
+ 0x0278, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IO (Decode16,
+ 0x0678, // Range Minimum
+ 0x0678, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {5,6,7,10,11,12}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {1,3}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x03BC, // Range Minimum
+ 0x03BC, // Range Maximum
+ 0x01, // Alignment
+ 0x04, // Length
+ )
+ IO (Decode16,
+ 0x07BC, // Range Minimum
+ 0x07BC, // Range Maximum
+ 0x01, // Alignment
+ 0x04, // Length
+ )
+ IRQNoFlags ()
+ {5,6,7,10,11,12}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {1,3}
+ }
+ EndDependentFn ()
+ })
+ }
+
+ Device (NBRM)
+ {
+ Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_UID, 0x99) // _UID: Unique ID
+ Name (CRS, ResourceTemplate ()
+ {
+ })
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (CRS) /* \_SB_.PCI0.SBRG.NBRM.CRS_ */
+ }
+ }
+
+ Device (PIC)
+ {
+ Name (_HID, EisaId ("PNP0000") /* 8259-compatible Programmable Interrupt Controller */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0020, // Range Minimum
+ 0x0020, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x00A0, // Range Minimum
+ 0x00A0, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ IRQNoFlags ()
+ {2}
+ })
+ }
+
+ Device (DMAD)
+ {
+ Name (_HID, EisaId ("PNP0200") /* PC-class DMA Controller */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ DMA (Compatibility, BusMaster, Transfer8, )
+ {4}
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IO (Decode16,
+ 0x0081, // Range Minimum
+ 0x0081, // Range Maximum
+ 0x00, // Alignment
+ 0x03, // Length
+ )
+ IO (Decode16,
+ 0x0087, // Range Minimum
+ 0x0087, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0089, // Range Minimum
+ 0x0089, // Range Maximum
+ 0x00, // Alignment
+ 0x03, // Length
+ )
+ IO (Decode16,
+ 0x008F, // Range Minimum
+ 0x008F, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x00C0, // Range Minimum
+ 0x00C0, // Range Maximum
+ 0x00, // Alignment
+ 0x20, // Length
+ )
+ })
+ }
+
+ Device (TMR)
+ {
+ Name (_HID, EisaId ("PNP0100") /* PC-class System Timer */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0040, // Range Minimum
+ 0x0040, // Range Maximum
+ 0x00, // Alignment
+ 0x04, // Length
+ )
+ IRQNoFlags ()
+ {0}
+ })
+ }
+
+ Device (RTC0)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+
+ Device (SPKR)
+ {
+ Name (_HID, EisaId ("PNP0800") /* Microsoft Sound System Compatible Device */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0061, // Range Minimum
+ 0x0061, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ })
+ }
+
+ Device (RMSC)
+ {
+ Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (CRS1, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0010, // Range Minimum
+ 0x0010, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IO (Decode16,
+ 0x0022, // Range Minimum
+ 0x0022, // Range Maximum
+ 0x00, // Alignment
+ 0x1E, // Length
+ )
+ IO (Decode16,
+ 0x0044, // Range Minimum
+ 0x0044, // Range Maximum
+ 0x00, // Alignment
+ 0x1C, // Length
+ )
+ IO (Decode16,
+ 0x0062, // Range Minimum
+ 0x0062, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0065, // Range Minimum
+ 0x0065, // Range Maximum
+ 0x00, // Alignment
+ 0x0B, // Length
+ )
+ IO (Decode16,
+ 0x0072, // Range Minimum
+ 0x0072, // Range Maximum
+ 0x00, // Alignment
+ 0x0E, // Length
+ )
+ IO (Decode16,
+ 0x0080, // Range Minimum
+ 0x0080, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0084, // Range Minimum
+ 0x0084, // Range Maximum
+ 0x00, // Alignment
+ 0x03, // Length
+ )
+ IO (Decode16,
+ 0x0088, // Range Minimum
+ 0x0088, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x008C, // Range Minimum
+ 0x008C, // Range Maximum
+ 0x00, // Alignment
+ 0x03, // Length
+ )
+ IO (Decode16,
+ 0x0090, // Range Minimum
+ 0x0090, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IO (Decode16,
+ 0x00A2, // Range Minimum
+ 0x00A2, // Range Maximum
+ 0x00, // Alignment
+ 0x1E, // Length
+ )
+ IO (Decode16,
+ 0x00E0, // Range Minimum
+ 0x00E0, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IO (Decode16,
+ 0x04D0, // Range Minimum
+ 0x04D0, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ })
+ Name (CRS2, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0010, // Range Minimum
+ 0x0010, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IO (Decode16,
+ 0x0022, // Range Minimum
+ 0x0022, // Range Maximum
+ 0x00, // Alignment
+ 0x1E, // Length
+ )
+ IO (Decode16,
+ 0x0044, // Range Minimum
+ 0x0044, // Range Maximum
+ 0x00, // Alignment
+ 0x1C, // Length
+ )
+ IO (Decode16,
+ 0x0072, // Range Minimum
+ 0x0072, // Range Maximum
+ 0x00, // Alignment
+ 0x0E, // Length
+ )
+ IO (Decode16,
+ 0x0080, // Range Minimum
+ 0x0080, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0084, // Range Minimum
+ 0x0084, // Range Maximum
+ 0x00, // Alignment
+ 0x03, // Length
+ )
+ IO (Decode16,
+ 0x0088, // Range Minimum
+ 0x0088, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x008C, // Range Minimum
+ 0x008C, // Range Maximum
+ 0x00, // Alignment
+ 0x03, // Length
+ )
+ IO (Decode16,
+ 0x0090, // Range Minimum
+ 0x0090, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IO (Decode16,
+ 0x00A2, // Range Minimum
+ 0x00A2, // Range Maximum
+ 0x00, // Alignment
+ 0x1E, // Length
+ )
+ IO (Decode16,
+ 0x00E0, // Range Minimum
+ 0x00E0, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IO (Decode16,
+ 0x04D0, // Range Minimum
+ 0x04D0, // Range Maximum
+ 0x00, // Alignment
+ 0x02, // Length
+ )
+ })
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ If ((MBEC & 0xFFFF))
+ {
+ Return (CRS1) /* \_SB_.PCI0.SBRG.RMSC.CRS1 */
+ }
+ Else
+ {
+ Return (CRS2) /* \_SB_.PCI0.SBRG.RMSC.CRS2 */
+ }
+ }
+ }
+
+ Device (COPR)
+ {
+ Name (_HID, EisaId ("PNP0C04") /* x87-compatible Floating Point Processing Unit */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x00F0, // Range Minimum
+ 0x00F0, // Range Maximum
+ 0x00, // Alignment
+ 0x10, // Length
+ )
+ IRQNoFlags ()
+ {13}
+ })
+ }
+
+ Scope (^^PCI0)
+ {
+ Name (SLIC, Buffer (0x9E)
+ {
+ "812713457198Genuine NVIDIA Certified SLI Ready Motherboard for MSI Z77A-GD65 33f1-Copyright 2011 NVIDIA Corporation All Rights Reserved-231089828765(R)"
+ })
+ Device (WMI1)
+ {
+ Name (_HID, "pnp0c14") // _HID: Hardware ID
+ Name (_UID, "MXM2") // _UID: Unique ID
+ Name (_WDG, Buffer (0x14)
+ {
+ /* 0000 */ 0x3C, 0x5C, 0xCB, 0xF6, 0xAE, 0x9C, 0xBD, 0x4E, /* <\.....N */
+ /* 0008 */ 0xB5, 0x77, 0x93, 0x1E, 0xA3, 0x2A, 0x2C, 0xC0, /* .w...*,. */
+ /* 0010 */ 0x4D, 0x58, 0x01, 0x02 /* MX.. */
+ })
+ Method (WMMX, 3, NotSerialized)
+ {
+ CreateDWordField (Arg2, Zero, FUNC)
+ If ((FUNC == 0x41494C53))
+ {
+ Return (SLIC) /* \_SB_.PCI0.SLIC */
+ }
+
+ Return (Zero)
+ }
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Name (LUCD, Buffer (0x7D)
+ {
+ /* 0000 */ 0x4C, 0x75, 0x63, 0x69, 0x64, 0x4C, 0x6F, 0x67, /* LucidLog */
+ /* 0008 */ 0x69, 0x78, 0x00, 0x68, 0x00, 0x01, 0x00, 0x01, /* ix.h.... */
+ /* 0010 */ 0x00, 0x00, 0x00, 0xFD, 0xC6, 0x38, 0x37, 0x32, /* .....872 */
+ /* 0018 */ 0x36, 0x65, 0x33, 0x36, 0x65, 0x39, 0x64, 0x36, /* 6e36e9d6 */
+ /* 0020 */ 0x64, 0x35, 0x33, 0x36, 0x34, 0x36, 0x33, 0x39, /* d5364639 */
+ /* 0028 */ 0x30, 0x64, 0x34, 0x39, 0x35, 0x62, 0x34, 0x63, /* 0d495b4c */
+ /* 0030 */ 0x65, 0x39, 0x64, 0x63, 0x31, 0x33, 0x36, 0x30, /* e9dc1360 */
+ /* 0038 */ 0x64, 0x33, 0x32, 0x35, 0x62, 0x39, 0x38, 0x31, /* d325b981 */
+ /* 0040 */ 0x33, 0x61, 0x31, 0x31, 0x30, 0x31, 0x61, 0x66, /* 3a1101af */
+ /* 0048 */ 0x61, 0x32, 0x36, 0x31, 0x36, 0x30, 0x39, 0x35, /* a2616095 */
+ /* 0050 */ 0x35, 0x66, 0x64, 0x66, 0x66, 0x30, 0x30, 0x30, /* 5fdff000 */
+ /* 0058 */ 0x30, 0x32, 0x36, 0x36, 0x44, 0x63, 0x65, 0x64, /* 0266Dced */
+ /* 0060 */ 0x31, 0x36, 0x35, 0x31, 0x36, 0x33, 0x65, 0x35, /* 165163e5 */
+ /* 0068 */ 0x31, 0x65, 0x30, 0x36, 0x65, 0x30, 0x31, 0x64, /* 1e06e01d */
+ /* 0070 */ 0x63, 0x34, 0x34, 0x63, 0x33, 0x35, 0x66, 0x65, /* c44c35fe */
+ /* 0078 */ 0x61, 0x33, 0x65, 0x61, 0x66 /* a3eaf */
+ })
+ }
+ }
+
+ Device (P0PC)
+ {
+ Name (_ADR, 0x00140004) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x03, 0x04))
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (AR0C) /* \_SB_.AR0C */
+ }
+
+ Return (PR0C) /* \_SB_.PR0C */
+ }
+ }
+
+ Device (OHC1)
+ {
+ Name (_ADR, 0x00120000) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x0B, 0x04))
+ }
+ }
+
+ Device (EHC1)
+ {
+ Name (_ADR, 0x00120002) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x0B, 0x04))
+ }
+ }
+
+ Device (OHC2)
+ {
+ Name (_ADR, 0x00130000) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x0B, 0x04))
+ }
+ }
+
+ Device (EHC2)
+ {
+ Name (_ADR, 0x00130002) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x0B, 0x04))
+ }
+ }
+
+ Device (OHC3)
+ {
+ Name (_ADR, 0x00160000) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x0B, 0x04))
+ }
+ }
+
+ Device (EHC3)
+ {
+ Name (_ADR, 0x00160002) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x0B, 0x04))
+ }
+ }
+
+ Device (OHC4)
+ {
+ Name (_ADR, 0x00140005) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x0B, 0x04))
+ }
+ }
+
+ Device (XHC0)
+ {
+ Name (_ADR, 0x00100000) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x0B, 0x04))
+ }
+ }
+
+ Device (XHC1)
+ {
+ Name (_ADR, 0x00100001) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x0B, 0x04))
+ }
+ }
+
+ Device (SATA)
+ {
+ Name (_ADR, 0x00110000) // _ADR: Address
+ Method (_INI, 0, NotSerialized) // _INI: Initialize
+ {
+ }
+
+ OperationRegion (SACS, PCI_Config, Zero, 0x40)
+ Field (SACS, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x24),
+ STB5, 32
+ }
+
+ Name (SPTM, Buffer (0x14)
+ {
+ /* 0000 */ 0x78, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, /* x....... */
+ /* 0008 */ 0x78, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, /* x....... */
+ /* 0010 */ 0x1F, 0x00, 0x00, 0x00 /* .... */
+ })
+ Device (PRID)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Method (_GTM, 0, NotSerialized) // _GTM: Get Timing Mode
+ {
+ Return (SPTM) /* \_SB_.PCI0.SATA.SPTM */
+ }
+
+ Method (_STM, 3, NotSerialized) // _STM: Set Timing Mode
+ {
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((STCL == 0x0101))
+ {
+ Local1 = 0x0F
+ }
+ Else
+ {
+ Local1 = Zero
+ }
+
+ Return (Local1)
+ }
+
+ Name (PRIS, Zero)
+ Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
+ {
+ OperationRegion (BAR, SystemMemory, STB5, 0x0400)
+ Field (BAR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x120),
+ , 7,
+ PMBY, 1,
+ Offset (0x128),
+ PMS0, 4,
+ Offset (0x129),
+ PMS1, 4,
+ Offset (0x220),
+ , 7,
+ PSBY, 1,
+ Offset (0x228),
+ PSS0, 4,
+ Offset (0x229),
+ PSS1, 4,
+ Offset (0x2A0),
+ , 7
+ }
+
+ If (((OSVR == 0x06) || (OSVR == 0x04)))
+ {
+ If (PMS1)
+ {
+ Local0 = 0x32
+ While (((PMBY == One) && Local0))
+ {
+ Sleep (0xFA)
+ Local0--
+ }
+ }
+
+ If (PSS1)
+ {
+ Local0 = 0x32
+ While (((PSBY == One) && Local0))
+ {
+ Sleep (0xFA)
+ Local0--
+ }
+ }
+ }
+
+ PRIS = Zero
+ }
+
+ Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
+ {
+ PRIS = 0x03
+ }
+
+ Method (_PSC, 0, NotSerialized) // _PSC: Power State Current
+ {
+ Return (PRIS) /* \_SB_.PCI0.SATA.PRID.PRIS */
+ }
+
+ Device (P_D0)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ OperationRegion (BAR, SystemMemory, STB5, 0x0400)
+ Field (BAR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x128),
+ PMS0, 4,
+ Offset (0x129),
+ PMS1, 4
+ }
+
+ If (~(PMS1 == Zero))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (Zero)
+ }
+ }
+
+ Name (S12P, Zero)
+ Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
+ {
+ OperationRegion (BAR, SystemMemory, STB5, 0x0400)
+ Field (BAR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x120),
+ , 7,
+ PMBY, 1
+ }
+
+ Local0 = 0x32
+ While (((PMBY == One) && Local0))
+ {
+ Sleep (0xFA)
+ Local0--
+ }
+
+ S12P = Zero
+ }
+
+ Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
+ {
+ S12P = 0x03
+ }
+
+ Method (_PSC, 0, NotSerialized) // _PSC: Power State Current
+ {
+ Return (S12P) /* \_SB_.PCI0.SATA.PRID.P_D0.S12P */
+ }
+ }
+
+ Device (P_D1)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ OperationRegion (BAR, SystemMemory, STB5, 0x0400)
+ Field (BAR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x228),
+ PSS0, 4,
+ Offset (0x229),
+ PSS1, 4
+ }
+
+ If (~(PSS1 == Zero))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (Zero)
+ }
+ }
+
+ Name (S12P, Zero)
+ Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
+ {
+ OperationRegion (BAR, SystemMemory, STB5, 0x0400)
+ Field (BAR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x220),
+ , 7,
+ PSBY, 1
+ }
+
+ Local0 = 0x32
+ While (((PSBY == One) && Local0))
+ {
+ Sleep (0xFA)
+ Local0--
+ }
+
+ S12P = Zero
+ }
+
+ Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
+ {
+ S12P = 0x03
+ }
+
+ Method (_PSC, 0, NotSerialized) // _PSC: Power State Current
+ {
+ Return (S12P) /* \_SB_.PCI0.SATA.PRID.P_D1.S12P */
+ }
+ }
+ }
+
+ Device (SECD)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Method (_GTM, 0, NotSerialized) // _GTM: Get Timing Mode
+ {
+ Return (SPTM) /* \_SB_.PCI0.SATA.SPTM */
+ }
+
+ Method (_STM, 3, NotSerialized) // _STM: Set Timing Mode
+ {
+ }
+
+ Name (SECS, Zero)
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((STCL == 0x0101))
+ {
+ Local1 = 0x0F
+ }
+ Else
+ {
+ Local1 = Zero
+ }
+
+ Return (Local1)
+ }
+
+ Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
+ {
+ OperationRegion (BAR, SystemMemory, STB5, 0x0400)
+ Field (BAR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x1A0),
+ , 7,
+ SMBY, 1,
+ Offset (0x1A8),
+ SMS0, 4,
+ Offset (0x1A9),
+ SMS1, 4,
+ Offset (0x2A0),
+ , 7,
+ SSBY, 1,
+ Offset (0x2A8),
+ SSS0, 4,
+ Offset (0x2A9),
+ SSS1, 4,
+ Offset (0x2AC)
+ }
+
+ If (((OSVR == 0x06) || (OSVR == 0x04)))
+ {
+ If (SMS1)
+ {
+ Local0 = 0x32
+ While (((SMBY == One) && Local0))
+ {
+ Sleep (0xFA)
+ Local0--
+ }
+ }
+
+ If (SSS1)
+ {
+ Local0 = 0x32
+ While (((SSBY == One) && Local0))
+ {
+ Sleep (0xFA)
+ Local0--
+ }
+ }
+ }
+
+ SECS = Zero
+ }
+
+ Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
+ {
+ SECS = 0x03
+ }
+
+ Method (_PSC, 0, NotSerialized) // _PSC: Power State Current
+ {
+ Return (SECS) /* \_SB_.PCI0.SATA.SECD.SECS */
+ }
+
+ Device (S_D0)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ OperationRegion (BAR, SystemMemory, STB5, 0x0400)
+ Field (BAR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x1A8),
+ SMS0, 4,
+ Offset (0x1A9),
+ SMS1, 4
+ }
+
+ If (~(SMS1 == Zero))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (Zero)
+ }
+ }
+
+ Name (S12P, Zero)
+ Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
+ {
+ OperationRegion (BAR, SystemMemory, STB5, 0x1000)
+ Field (BAR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x1A0),
+ , 7,
+ SMBY, 1
+ }
+
+ Local0 = 0x32
+ While (((SMBY == One) && Local0))
+ {
+ Sleep (0xFA)
+ Local0--
+ }
+
+ S12P = Zero
+ }
+
+ Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
+ {
+ S12P = 0x03
+ }
+
+ Method (_PSC, 0, NotSerialized) // _PSC: Power State Current
+ {
+ Return (S12P) /* \_SB_.PCI0.SATA.SECD.S_D0.S12P */
+ }
+ }
+
+ Device (S_D1)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ OperationRegion (BAR, SystemMemory, STB5, 0x0400)
+ Field (BAR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x2A8),
+ SSS0, 4,
+ Offset (0x2A9),
+ SSS1, 4
+ }
+
+ If (~(SSS1 == Zero))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (Zero)
+ }
+ }
+
+ Name (S12P, Zero)
+ Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
+ {
+ OperationRegion (BAR, SystemMemory, STB5, 0x0400)
+ Field (BAR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x2A0),
+ , 7,
+ SSBY, 1
+ }
+
+ Local0 = 0x32
+ While (((SSBY == One) && Local0))
+ {
+ Sleep (0xFA)
+ Local0--
+ }
+
+ S12P = Zero
+ }
+
+ Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
+ {
+ S12P = 0x03
+ }
+
+ Method (_PSC, 0, NotSerialized) // _PSC: Power State Current
+ {
+ Return (S12P) /* \_SB_.PCI0.SATA.SECD.S_D1.S12P */
+ }
+ }
+ }
+ }
+
+ Device (PE20)
+ {
+ Name (_ADR, 0x00150000) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x0F, 0x04))
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (AR20) /* \_SB_.AR20 */
+ }
+
+ Return (PR20) /* \_SB_.PR20 */
+ }
+ }
+
+ Device (PE21)
+ {
+ Name (_ADR, 0x00150001) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x10, 0x04))
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (AR21) /* \_SB_.AR21 */
+ }
+
+ Return (PR21) /* \_SB_.PR21 */
+ }
+ }
+
+ Device (PE22)
+ {
+ Name (_ADR, 0x00150002) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x11, 0x04))
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (AR22) /* \_SB_.AR22 */
+ }
+
+ Return (PR22) /* \_SB_.PR22 */
+ }
+ }
+
+ Device (PE23)
+ {
+ Name (_ADR, 0x00150003) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x12, 0x04))
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (AR23) /* \_SB_.AR23 */
+ }
+
+ Return (PR23) /* \_SB_.PR23 */
+ }
+ }
+
+ Device (BR12)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x18, 0x04))
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (AR12) /* \_SB_.AR12 */
+ }
+
+ Return (PR12) /* \_SB_.PR12 */
+ }
+ }
+
+ Device (BR13)
+ {
+ Name (_ADR, 0x00030000) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x18, 0x04))
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (AR13) /* \_SB_.AR13 */
+ }
+
+ Return (PR13) /* \_SB_.PR13 */
+ }
+ }
+
+ Device (BR14)
+ {
+ Name (_ADR, 0x00040000) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x18, 0x04))
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (AR14) /* \_SB_.AR14 */
+ }
+
+ Return (PR14) /* \_SB_.PR14 */
+ }
+ }
+
+ Device (BR15)
+ {
+ Name (_ADR, 0x00050000) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x18, 0x04))
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (AR15) /* \_SB_.AR15 */
+ }
+
+ Return (PR15) /* \_SB_.PR15 */
+ }
+ }
+
+ Device (BR16)
+ {
+ Name (_ADR, 0x00060000) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x18, 0x04))
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (AR16) /* \_SB_.AR16 */
+ }
+
+ Return (PR16) /* \_SB_.PR16 */
+ }
+ }
+
+ Device (BR17)
+ {
+ Name (_ADR, 0x00070000) // _ADR: Address
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x18, 0x04))
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (AR17) /* \_SB_.AR17 */
+ }
+
+ Return (PR17) /* \_SB_.PR17 */
+ }
+ }
+ }
+
+ Scope (\_GPE)
+ {
+ Method (_L1B, 0, NotSerialized) // _Lxx: Level-Triggered GPE
+ {
+ Notify (\_SB.PCI0.SBAZ, 0x02) // Device Wake
+ Notify (\_SB.PWRB, 0x02) // Device Wake
+ }
+
+ Method (_L1D, 0, NotSerialized) // _Lxx: Level-Triggered GPE
+ {
+ \_SB.PCI0.SBRG.SIOH ()
+ Notify (\_SB.PWRB, 0x02) // Device Wake
+ }
+
+ Method (_L03, 0, NotSerialized) // _Lxx: Level-Triggered GPE
+ {
+ Notify (\_SB.PCI0.P0PC, 0x02) // Device Wake
+ Notify (\_SB.PWRB, 0x02) // Device Wake
+ }
+
+ Method (_L0B, 0, NotSerialized) // _Lxx: Level-Triggered GPE
+ {
+ Notify (\_SB.PCI0.OHC1, 0x02) // Device Wake
+ Notify (\_SB.PCI0.EHC1, 0x02) // Device Wake
+ Notify (\_SB.PCI0.OHC2, 0x02) // Device Wake
+ Notify (\_SB.PCI0.EHC2, 0x02) // Device Wake
+ Notify (\_SB.PCI0.OHC3, 0x02) // Device Wake
+ Notify (\_SB.PCI0.EHC3, 0x02) // Device Wake
+ Notify (\_SB.PCI0.OHC4, 0x02) // Device Wake
+ Notify (\_SB.PCI0.XHC0, 0x02) // Device Wake
+ Notify (\_SB.PCI0.XHC1, 0x02) // Device Wake
+ Notify (\_SB.PWRB, 0x02) // Device Wake
+ }
+
+ Method (_L0F, 0, NotSerialized) // _Lxx: Level-Triggered GPE
+ {
+ Notify (\_SB.PCI0.PE20, 0x02) // Device Wake
+ Notify (\_SB.PWRB, 0x02) // Device Wake
+ }
+
+ Method (_L10, 0, NotSerialized) // _Lxx: Level-Triggered GPE
+ {
+ Notify (\_SB.PCI0.PE21, 0x02) // Device Wake
+ Notify (\_SB.PWRB, 0x02) // Device Wake
+ }
+
+ Method (_L11, 0, NotSerialized) // _Lxx: Level-Triggered GPE
+ {
+ Notify (\_SB.PCI0.PE22, 0x02) // Device Wake
+ Notify (\_SB.PWRB, 0x02) // Device Wake
+ }
+
+ Method (_L12, 0, NotSerialized) // _Lxx: Level-Triggered GPE
+ {
+ Notify (\_SB.PCI0.PE23, 0x02) // Device Wake
+ Notify (\_SB.PWRB, 0x02) // Device Wake
+ }
+
+ Method (_L18, 0, NotSerialized) // _Lxx: Level-Triggered GPE
+ {
+ Notify (\_SB.PCI0.BR12, 0x02) // Device Wake
+ Notify (\_SB.PCI0.BR13, 0x02) // Device Wake
+ Notify (\_SB.PCI0.BR14, 0x02) // Device Wake
+ Notify (\_SB.PCI0.BR15, 0x02) // Device Wake
+ Notify (\_SB.PCI0.BR16, 0x02) // Device Wake
+ Notify (\_SB.PCI0.BR17, 0x02) // Device Wake
+ Notify (\_SB.PWRB, 0x02) // Device Wake
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C") /* Power Button Device */) // _HID: Hardware ID
+ Name (_UID, 0xAA) // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ Return (GPRW (0x1D, 0x03))
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ OperationRegion (PIRQ, SystemIO, 0x0C00, 0x02)
+ Field (PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PIDX, 8,
+ PDAT, 8
+ }
+
+ IndexField (PIDX, PDAT, ByteAcc, NoLock, Preserve)
+ {
+ PIRA, 8,
+ PIRB, 8,
+ PIRC, 8,
+ PIRD, 8,
+ PIRE, 8,
+ PIRF, 8,
+ PIRG, 8,
+ PIRH, 8,
+ Offset (0x10),
+ PIRS, 8,
+ Offset (0x13),
+ HDAD, 8,
+ Offset (0x15),
+ GEC, 8,
+ Offset (0x30),
+ USB1, 8,
+ USB2, 8,
+ USB3, 8,
+ USB4, 8,
+ USB5, 8,
+ USB6, 8,
+ USB7, 8,
+ Offset (0x40),
+ IDE, 8,
+ SATA, 8,
+ Offset (0x50),
+ GPP0, 8,
+ GPP1, 8,
+ GPP2, 8,
+ GPP3, 8
+ }
+
+ OperationRegion (KBDD, SystemIO, 0x64, One)
+ Field (KBDD, ByteAcc, NoLock, Preserve)
+ {
+ PD64, 8
+ }
+
+ Method (IRQC, 0, NotSerialized)
+ {
+ INTA (0x1F)
+ INTB (0x1F)
+ INTC (0x1F)
+ INTD (0x1F)
+ Local1 = PD64 /* \_SB_.PD64 */
+ PIRE = 0x1F
+ PIRF = 0x1F
+ PIRG = 0x1F
+ PIRH = 0x1F
+ }
+
+ Method (INTA, 1, NotSerialized)
+ {
+ PIRA = Arg0
+ HDAD = Arg0
+ GEC = Arg0
+ GPP0 = Arg0
+ GPP0 = Arg0
+ }
+
+ Method (INTB, 1, NotSerialized)
+ {
+ PIRB = Arg0
+ USB2 = Arg0
+ USB4 = Arg0
+ USB6 = Arg0
+ GPP1 = Arg0
+ IDE = Arg0
+ }
+
+ Method (INTC, 1, NotSerialized)
+ {
+ PIRC = Arg0
+ USB1 = Arg0
+ USB3 = Arg0
+ USB5 = Arg0
+ USB7 = Arg0
+ GPP2 = Arg0
+ }
+
+ Method (INTD, 1, NotSerialized)
+ {
+ PIRD = Arg0
+ SATA = Arg0
+ GPP3 = Arg0
+ }
+
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {15}
+ })
+ Name (IPRA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {5,10,11}
+ })
+ Name (IPRB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {5,10,11}
+ })
+ Name (IPRC, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {5,10,11}
+ })
+ Name (IPRD, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {5,10,11}
+ })
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (PIRA)
+ {
+ Return (0x0B)
+ }
+ Else
+ {
+ Return (0x09)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized) // _PRS: Possible Resource Settings
+ {
+ Return (PRSA) /* \_SB_.PRSA */
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ INTA (0x1F)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateWordField (BUFA, One, IRQX)
+ IRQX = (One << PIRA) /* \_SB_.PIRA */
+ Return (BUFA) /* \_SB_.BUFA */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRA)
+ FindSetRightBit (IRA, Local0)
+ Local0--
+ INTA (Local0)
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (PIRB)
+ {
+ Return (0x0B)
+ }
+ Else
+ {
+ Return (0x09)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized) // _PRS: Possible Resource Settings
+ {
+ Return (PRSB) /* \_SB_.PRSB */
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ INTB (0x1F)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateWordField (BUFA, One, IRQX)
+ IRQX = (One << PIRB) /* \_SB_.PIRB */
+ Return (BUFA) /* \_SB_.BUFA */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRA)
+ FindSetRightBit (IRA, Local0)
+ Local0--
+ INTB (Local0)
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (PIRC)
+ {
+ Return (0x0B)
+ }
+ Else
+ {
+ Return (0x09)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized) // _PRS: Possible Resource Settings
+ {
+ Return (PRSC) /* \_SB_.PRSC */
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ INTC (0x1F)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateWordField (BUFA, One, IRQX)
+ IRQX = (One << PIRC) /* \_SB_.PIRC */
+ Return (BUFA) /* \_SB_.BUFA */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRA)
+ FindSetRightBit (IRA, Local0)
+ Local0--
+ INTC (Local0)
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (PIRD)
+ {
+ Return (0x0B)
+ }
+ Else
+ {
+ Return (0x09)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized) // _PRS: Possible Resource Settings
+ {
+ Return (PRSD) /* \_SB_.PRSD */
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ INTD (0x1F)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateWordField (BUFA, One, IRQX)
+ IRQX = (One << PIRD) /* \_SB_.PIRD */
+ Return (BUFA) /* \_SB_.BUFA */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRA)
+ FindSetRightBit (IRA, Local0)
+ Local0--
+ INTD (Local0)
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (PIRE)
+ {
+ Return (0x0B)
+ }
+ Else
+ {
+ Return (0x09)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized) // _PRS: Possible Resource Settings
+ {
+ Return (PRSE) /* \_SB_.PRSE */
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PIRE = 0x1F
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateWordField (BUFA, One, IRQX)
+ IRQX = (One << PIRE) /* \_SB_.PIRE */
+ Return (BUFA) /* \_SB_.BUFA */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRA)
+ FindSetRightBit (PIRE, Local0)
+ Local0--
+ PIRE = Local0
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (PIRF)
+ {
+ Return (0x0B)
+ }
+ Else
+ {
+ Return (0x09)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized) // _PRS: Possible Resource Settings
+ {
+ Return (PRSF) /* \_SB_.PRSF */
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PIRF = 0x1F
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateWordField (BUFA, One, IRQX)
+ IRQX = (One << PIRF) /* \_SB_.PIRF */
+ Return (BUFA) /* \_SB_.BUFA */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRA)
+ FindSetRightBit (IRA, Local0)
+ Local0--
+ PIRF = Local0
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (PIRG)
+ {
+ Return (0x0B)
+ }
+ Else
+ {
+ Return (0x09)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized) // _PRS: Possible Resource Settings
+ {
+ Return (PRSG) /* \_SB_.PRSG */
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PIRG = 0x1F
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateWordField (BUFA, One, IRQX)
+ IRQX = (One << PIRG) /* \_SB_.PIRG */
+ Return (BUFA) /* \_SB_.BUFA */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRA)
+ FindSetRightBit (IRA, Local0)
+ Local0--
+ PIRG = Local0
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (PIRH)
+ {
+ Return (0x0B)
+ }
+ Else
+ {
+ Return (0x09)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized) // _PRS: Possible Resource Settings
+ {
+ Return (PRSH) /* \_SB_.PRSH */
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PIRH = 0x1F
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateWordField (BUFA, One, IRQX)
+ IRQX = (One << PIRH) /* \_SB_.PIRH */
+ Return (BUFA) /* \_SB_.BUFA */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRA)
+ FindSetRightBit (IRA, Local0)
+ Local0--
+ PIRH = Local0
+ }
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ Name (SUPP, Zero)
+ Name (CTRL, Zero)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */
+ CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ If (((SUPP & 0x16) != 0x16))
+ {
+ (CTRL & 0x1E)
+ }
+
+ If (!PEHP)
+ {
+ CTRL &= 0x1E
+ }
+
+ If (!SHPC)
+ {
+ CTRL &= 0x1D
+ }
+
+ If (!PEPM)
+ {
+ CTRL &= 0x1B
+ }
+
+ If (!PEER)
+ {
+ CTRL &= 0x15
+ }
+
+ If (!PECS)
+ {
+ CTRL &= 0x0F
+ }
+
+ If (OSCF)
+ {
+ If (~(CDW1 & One))
+ {
+ If ((CTRL & One)) {}
+ If ((CTRL & 0x04))
+ {
+ EPNM = One
+ }
+ Else
+ {
+ EPNM = Zero
+ }
+
+ If ((CTRL & 0x10)) {}
+ }
+ }
+
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != CTRL))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = CTRL /* \_SB_.PCI0._OSC.CTRL */
+ Return (Arg3)
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ Return (Arg3)
+ }
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Method (_INI, 0, NotSerialized) // _INI: Initialize
+ {
+ OSFL ()
+ If ((RVID <= 0x13)) {}
+ If (IMCS)
+ {
+ IBWE ()
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Scope (SBRG)
+ {
+ Method (RRIO, 4, NotSerialized)
+ {
+ Debug = "RRIO"
+ }
+
+ Method (RDMA, 3, NotSerialized)
+ {
+ Debug = "rDMA"
+ }
+ }
+ }
+ }
+
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ _Y24)
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (((HPAD & 0x03) == 0x03))
+ {
+ If ((OSVR >= 0x0C))
+ {
+ Return (0x0F)
+ }
+
+ HPAD = (HPAD & 0xFFFFFFE0)
+ Return (One)
+ }
+
+ Return (One)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ CreateDWordField (CRS, \HPET._Y24._BAS, HPT) // _BAS: Base Address
+ HPT = 0xFED00000
+ Return (CRS) /* \HPET.CRS_ */
+ }
+ }
+
+ Scope (_PR)
+ {
+ OperationRegion (SSDT, SystemMemory, 0xFFFF0000, 0xFFFF)
+ Name (DCOR, 0x02)
+ Name (TBLD, 0x04)
+ Name (NPSS, 0x05)
+ Name (HNDL, 0x80000000)
+ Name (APSS, Package (0x0A)
+ {
+ Package (0x06)
+ {
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ },
+
+ Package (0x06)
+ {
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ },
+
+ Package (0x06)
+ {
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ },
+
+ Package (0x06)
+ {
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ },
+
+ Package (0x06)
+ {
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ },
+
+ Package (0x06)
+ {
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ },
+
+ Package (0x06)
+ {
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ },
+
+ Package (0x06)
+ {
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ },
+
+ Package (0x06)
+ {
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ },
+
+ Package (0x06)
+ {
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ }
+ })
+ Processor (P000, 0x01, 0x00000810, 0x06)
+ {
+ Name (TYPE, 0x80000000)
+ Method (_PDC, 1, NotSerialized) // _PDC: Processor Driver Capabilities
+ {
+ CreateDWordField (Arg0, 0x08, DAT0)
+ TYPE = DAT0 /* \_PR_.P000._PDC.DAT0 */
+ If (((TBLD == Zero) && (NPSS != Zero)))
+ {
+ If ((((TYPE & 0x1B) == 0x1B) || (DCOR == Zero)))
+ {
+ TBLD = One
+ Load (SSDT, HNDL) /* \_PR_.HNDL */
+ }
+ }
+ }
+ }
+
+ Processor (P001, 0x02, 0x00000810, 0x06)
+ {
+ Name (TYPE, 0x80000000)
+ Method (_PDC, 1, NotSerialized) // _PDC: Processor Driver Capabilities
+ {
+ CreateDWordField (Arg0, 0x08, DAT0)
+ TYPE = DAT0 /* \_PR_.P001._PDC.DAT0 */
+ If (((TBLD == Zero) && (NPSS != Zero)))
+ {
+ If ((((TYPE & 0x1B) == 0x1B) || (DCOR == Zero)))
+ {
+ TBLD = One
+ Load (SSDT, HNDL) /* \_PR_.HNDL */
+ }
+ }
+ }
+ }
+
+ Processor (P002, 0x03, 0x00000810, 0x06)
+ {
+ Name (TYPE, 0x80000000)
+ Method (_PDC, 1, NotSerialized) // _PDC: Processor Driver Capabilities
+ {
+ CreateDWordField (Arg0, 0x08, DAT0)
+ TYPE = DAT0 /* \_PR_.P002._PDC.DAT0 */
+ If (((TBLD == Zero) && (NPSS != Zero)))
+ {
+ If ((((TYPE & 0x1B) == 0x1B) || (DCOR == Zero)))
+ {
+ TBLD = One
+ Load (SSDT, HNDL) /* \_PR_.HNDL */
+ }
+ }
+ }
+ }
+
+ Processor (P003, 0x04, 0x00000810, 0x06)
+ {
+ Name (TYPE, 0x80000000)
+ Method (_PDC, 1, NotSerialized) // _PDC: Processor Driver Capabilities
+ {
+ CreateDWordField (Arg0, 0x08, DAT0)
+ TYPE = DAT0 /* \_PR_.P003._PDC.DAT0 */
+ If (((TBLD == Zero) && (NPSS != Zero)))
+ {
+ If ((((TYPE & 0x1B) == 0x1B) || (DCOR == Zero)))
+ {
+ TBLD = One
+ Load (SSDT, HNDL) /* \_PR_.HNDL */
+ }
+ }
+ }
+ }
+ }
+
+ Name (WOTB, Zero)
+ Name (WSSB, Zero)
+ Name (WAXB, Zero)
+ Method (_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep
+ {
+ DBG8 = Arg0
+ If (((Arg0 == 0x04) && (OSFL () == 0x02)))
+ {
+ Sleep (0x0BB8)
+ }
+
+ PTS (Arg0)
+ WAKP [Zero] = Zero
+ WAKP [One] = Zero
+ WSSB = ASSB /* \ASSB */
+ WOTB = AOTB /* \AOTB */
+ WAXB = AAXB /* \AAXB */
+ ASSB = Arg0
+ AOTB = OSFL ()
+ AAXB = Zero
+ \_SB.SLPS = One
+ }
+
+ Method (_WAK, 1, NotSerialized) // _WAK: Wake
+ {
+ DBG8 = (Arg0 << 0x04)
+ WAK (Arg0)
+ If (ASSB)
+ {
+ ASSB = WSSB /* \WSSB */
+ AOTB = WOTB /* \WOTB */
+ AAXB = WAXB /* \WAXB */
+ }
+
+ If (DerefOf (WAKP [Zero]))
+ {
+ WAKP [One] = Zero
+ }
+ Else
+ {
+ WAKP [One] = Arg0
+ }
+
+ Return (WAKP) /* \WAKP */
+ }
+
+ Device (OMSC)
+ {
+ Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_UID, 0x0E11) // _UID: Unique ID
+ }
+
+ Device (_SB.RMEM)
+ {
+ Name (_HID, EisaId ("PNP0C01") /* System Board */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ }
+
+ Device (_SB.TPM)
+ {
+ Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+ {
+ If (TCMF) {}
+ Else
+ {
+ Return (0x0201D824)
+ }
+ }
+
+ Name (_CID, EisaId ("PNP0C31")) // _CID: Compatible ID
+ Name (_STR, Unicode ("TPM 1.2 Device")) // _STR: Description String
+ Name (_UID, One) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xFED40000, // Range Minimum
+ 0xFED44FFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00005000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ OperationRegion (TMMB, SystemMemory, 0xFED40000, 0x5000)
+ Field (TMMB, ByteAcc, Lock, Preserve)
+ {
+ ACCS, 8,
+ Offset (0x18),
+ TSTA, 8,
+ TBCA, 8,
+ Offset (0xF00),
+ TVID, 16,
+ TDID, 16
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (TPMF)
+ {
+ Return (0x0F)
+ }
+
+ Return (Zero)
+ }
+ }
+
+ Scope (_SB.TPM)
+ {
+ OperationRegion (ASMI, SystemIO, SMIA, One)
+ Field (ASMI, ByteAcc, NoLock, Preserve)
+ {
+ INQ, 8
+ }
+
+ OperationRegion (BSMI, SystemIO, SMIB, One)
+ Field (BSMI, ByteAcc, NoLock, Preserve)
+ {
+ DAT, 8
+ }
+
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */))
+ {
+ Name (_T_0, Zero) // _T_x: Emitted by ASL Compiler
+ _T_0 = ToInteger (Arg2)
+ If ((_T_0 == Zero))
+ {
+ Return (Buffer (0x02)
+ {
+ 0xFF, 0x01 /* .. */
+ })
+ }
+ ElseIf ((_T_0 == One))
+ {
+ Return ("1.2")
+ }
+ ElseIf ((_T_0 == 0x02))
+ {
+ ToInteger (DerefOf (Arg3 [Zero]), TMF2) /* \TMF2 */
+ TMF1 = 0x12
+ DAT = TMF1 /* \TMF1 */
+ INQ = OFST /* \OFST */
+ If ((DAT == 0xFF))
+ {
+ Return (0x02)
+ }
+
+ DAT = TMF2 /* \TMF2 */
+ INQ = OFST /* \OFST */
+ If ((DAT == 0xFF))
+ {
+ Return (0x02)
+ }
+
+ If ((DAT == 0xF1))
+ {
+ Return (One)
+ }
+
+ Return (Zero)
+ }
+ ElseIf ((_T_0 == 0x03))
+ {
+ Name (PPI1, Package (0x02)
+ {
+ Zero,
+ Zero
+ })
+ DAT = 0x11
+ INQ = OFST /* \OFST */
+ If ((DAT == 0xFF))
+ {
+ Return (One)
+ }
+
+ PPI1 [One] = DAT /* \_SB_.TPM_.DAT_ */
+ Return (PPI1) /* \_SB_.TPM_._DSM.PPI1 */
+ }
+ ElseIf ((_T_0 == 0x04))
+ {
+ Return (TRST) /* \TRST */
+ }
+ ElseIf ((_T_0 == 0x05))
+ {
+ Name (PPI2, Package (0x03)
+ {
+ Zero,
+ Zero,
+ Zero
+ })
+ DAT = 0x21
+ INQ = OFST /* \OFST */
+ PPI2 [One] = DAT /* \_SB_.TPM_.DAT_ */
+ If ((DAT == 0xFF))
+ {
+ Return (0x02)
+ }
+
+ DAT = 0x31
+ INQ = OFST /* \OFST */
+ If ((DAT == 0xFF))
+ {
+ Return (0x02)
+ }
+
+ If ((DAT == 0xF0))
+ {
+ DAT = 0x51
+ INQ = OFST /* \OFST */
+ If ((DAT == 0xFF))
+ {
+ PPI2 [0x02] = 0xFFFFFFF0
+ Return (PPI2) /* \_SB_.TPM_._DSM.PPI2 */
+ }
+ }
+ ElseIf ((DAT == 0xF1))
+ {
+ DAT = 0x51
+ INQ = OFST /* \OFST */
+ If ((DAT == 0xFF))
+ {
+ PPI2 [0x02] = 0xFFFFFFF1
+ Return (PPI2) /* \_SB_.TPM_._DSM.PPI2 */
+ }
+ }
+ Else
+ {
+ PPI2 [0x02] = DAT /* \_SB_.TPM_.DAT_ */
+ }
+
+ Return (PPI2) /* \_SB_.TPM_._DSM.PPI2 */
+ }
+ ElseIf ((_T_0 == 0x06))
+ {
+ Return (0x03)
+ }
+ ElseIf ((_T_0 == 0x07))
+ {
+ ToInteger (DerefOf (Arg3 [Zero]), TMF2) /* \TMF2 */
+ TMF1 = 0x12
+ DAT = TMF1 /* \TMF1 */
+ INQ = OFST /* \OFST */
+ If ((DAT == 0xFF))
+ {
+ Return (0x02)
+ }
+
+ DAT = TMF2 /* \TMF2 */
+ INQ = OFST /* \OFST */
+ If ((DAT == 0xFF))
+ {
+ Return (0x02)
+ }
+
+ If ((DAT == 0xF1))
+ {
+ Return (One)
+ }
+
+ Return (Zero)
+ }
+ ElseIf ((_T_0 == 0x08))
+ {
+ ToInteger (DerefOf (Arg3 [Zero]), TMF2) /* \TMF2 */
+ TMF1 = 0x43
+ DAT = TMF1 /* \TMF1 */
+ INQ = OFST /* \OFST */
+ DAT = TMF2 /* \TMF2 */
+ INQ = OFST /* \OFST */
+ Return (DAT) /* \_SB_.TPM_.DAT_ */
+ }
+ Else
+ {
+ }
+ }
+ ElseIf ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))
+ {
+ Name (_T_1, Zero) // _T_x: Emitted by ASL Compiler
+ _T_1 = ToInteger (Arg2)
+ If ((_T_1 == Zero))
+ {
+ Return (Buffer (One)
+ {
+ 0x03 /* . */
+ })
+ }
+ ElseIf ((_T_1 == One))
+ {
+ TMF1 = 0x22
+ DAT = TMF1 /* \TMF1 */
+ INQ = OFST /* \OFST */
+ If ((DAT == 0xFF))
+ {
+ Return (0x02)
+ }
+
+ ToInteger (DerefOf (Arg3 [Zero]), TMF1) /* \TMF1 */
+ DAT = TMF1 /* \TMF1 */
+ INQ = OFST /* \OFST */
+ If ((DAT == 0xFF))
+ {
+ Return (0x02)
+ }
+
+ Return (Zero)
+ }
+ Else
+ {
+ }
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 /* . */
+ })
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (WMIO)
+ {
+ Mutex (WMIX, 0x01)
+ Name (_HID, "pnp0c14") // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (BUF4, Buffer (0x04)
+ {
+ 0x00, 0x00, 0x00, 0x00 /* .... */
+ })
+ CreateByteField (BUF4, Zero, BF00)
+ CreateByteField (BUF4, One, BF01)
+ CreateByteField (BUF4, 0x02, BF02)
+ CreateByteField (BUF4, 0x03, BF03)
+ Name (_WDG, Buffer (0x14)
+ {
+ /* 0000 */ 0xCE, 0x93, 0x05, 0xA8, 0x77, 0x23, 0xDA, 0x11, /* ....w#.. */
+ /* 0008 */ 0xB0, 0x12, 0xB6, 0x22, 0x20, 0x12, 0x07, 0x27, /* ..." ..' */
+ /* 0010 */ 0x4D, 0x49, 0x01, 0x02 /* MI.. */
+ })
+ OperationRegion (CMOS, SystemIO, 0x72, 0x02)
+ Field (CMOS, ByteAcc, NoLock, Preserve)
+ {
+ CMIN, 8,
+ CMDA, 8
+ }
+
+ IndexField (CMIN, CMDA, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xD9),
+ WDFH, 8
+ }
+
+ Method (WMMI, 3, NotSerialized)
+ {
+ If ((Arg1 == 0xD0))
+ {
+ BUF4 = Arg2
+ If ((BF00 == Zero))
+ {
+ BUF4 = Zero
+ BF00 = SMIP /* \SMIP */
+ BF02 = CISI /* \CISI */
+ Return (BUF4) /* \_SB_.WMIO.BUF4 */
+ }
+
+ Return (0xFFFFFFFF)
+ }
+
+ If ((Arg1 == 0xFB))
+ {
+ BUF4 = Arg2
+ If ((BF00 == Zero))
+ {
+ BUF4 = Zero
+ BF02 = One
+ Return (BUF4) /* \_SB_.WMIO.BUF4 */
+ }
+
+ If ((BF00 == One))
+ {
+ BUF4 = Zero
+ BF00 = SMIP /* \SMIP */
+ Return (BUF4) /* \_SB_.WMIO.BUF4 */
+ }
+
+ If ((BF00 == 0x02))
+ {
+ BUF4 = Zero
+ BF00 = FESI /* \FESI */
+ BF01 = FDSI /* \FDSI */
+ BF02 = FSSI /* \FSSI */
+ Return (BUF4) /* \_SB_.WMIO.BUF4 */
+ }
+
+ If ((BF00 == 0x03))
+ {
+ CMIN = 0xD9
+ BF00 = CMDA /* \_SB_.WMIO.CMDA */
+ If ((BF00 & One))
+ {
+ BF00 = One
+ Return (BUF4) /* \_SB_.WMIO.BUF4 */
+ }
+ Else
+ {
+ BF00 = Zero
+ Return (BUF4) /* \_SB_.WMIO.BUF4 */
+ }
+ }
+ }
+
+ Return (0xFFFFFFFF)
+ }
+ }
+ }
+
+ Name (_S0, Package (0x04) // _S0_: S0 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ If (SS3)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ 0x03,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ If (SS4)
+ {
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x04,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ 0x05,
+ Zero,
+ Zero,
+ Zero
+ })
+ Method (PTS, 1, NotSerialized)
+ {
+ If (Arg0)
+ {
+ SPTS (Arg0)
+ \_SB.PCI0.NPTS (Arg0)
+ \_SB.PCI0.SBRG.SIOS (Arg0)
+ }
+ }
+
+ Method (WAK, 1, NotSerialized)
+ {
+ SWAK (Arg0)
+ \_SB.PCI0.NWAK (Arg0)
+ \_SB.PCI0.SBRG.SIOW (Arg0)
+ }
+
+ Method (_SB._OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ Return (Arg3)
+ }
+}
+
diff --git a/src/mainboard/msi/ms7721/irq_tables.c b/src/mainboard/msi/ms7721/irq_tables.c
index 458c157..eeaf8d3 100644
--- a/src/mainboard/msi/ms7721/irq_tables.c
+++ b/src/mainboard/msi/ms7721/irq_tables.c
@@ -39,6 +39,7 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu;
}
+
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c
index 09d9455..4f00dad 100644
--- a/src/mainboard/msi/ms7721/mptable.c
+++ b/src/mainboard/msi/ms7721/mptable.c
@@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* IOMMU */
PCI_INT(0x0, 0x0, 0x0, 0x10);
diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c
index 0e502e7..9ae5d98 100644
--- a/src/mainboard/msi/ms7721/romstage.c
+++ b/src/mainboard/msi/ms7721/romstage.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2012 Rudolf Marek <r.marek at assembler.cz>
+ * Copyright (C) 2016 Renze Nicolai <renze at rnplus.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,13 +16,10 @@
*/
#include <northbridge/amd/agesa/agesawrapper.h>
-
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/stages.h>
-#include <cbmem.h>
-#include <console/console.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/amd/car.h>
#include <cpu/x86/bist.h>
@@ -31,18 +29,123 @@
#include <device/pnp_def.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <southbridge/amd/agesa/hudson/smbus.h>
+#include <superio/fintek/common/fintek.h>
+#include <superio/fintek/f71869ad/f71869ad.h>
#include <stdint.h>
#include <string.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8728f/it8728f.h>
+#include <cbmem.h>
+#include <console/console.h>
-#define MMIO_NON_POSTED_START 0xfed00000
-#define MMIO_NON_POSTED_END 0xfedfffff
+//#define MMIO_NON_POSTED_START 0xfed00000
+//#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO 0xFED80000
#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
-#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
+/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
+#define SUPERIO_ADDRESS 0x4e
+
+#define SERIAL_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_SP1)
+#define GPIO_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_GPIO)
+#define PP_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_PP)
+
+/*--- (TO-DO: Move super i/o code to super i/o section) ---*/
+
+#define FINTEK_ENTRY_KEY 0x87
+/* Enable configuration: pass entry key '0x87' into index port dev. */
+static void pnp_enter_conf_state(pnp_devfn_t dev)
+{
+ u16 port = dev >> 8;
+ outb(FINTEK_ENTRY_KEY, port);
+ outb(FINTEK_ENTRY_KEY, port);
+}
+
+#define FINTEK_EXIT_KEY 0xAA
+/* Disable configuration: pass exit key '0xAA' into index port dev. */
+static void pnp_exit_conf_state(pnp_devfn_t dev)
+{
+ u16 port = dev >> 8;
+ outb(FINTEK_EXIT_KEY, port);
+}
+
+static void parport_init(pnp_devfn_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_write_config(dev, 0x30, 0x01);
+ pnp_write_config(dev, 0x60, 0x03);
+ pnp_write_config(dev, 0x61, 0x78);
+ pnp_write_config(dev, 0x70, 0x05);
+ pnp_write_config(dev, 0x74, 0x03);
+ pnp_write_config(dev, 0xF0, 0x44);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+
+static void gpio_init(pnp_devfn_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+
+ pnp_write_config(dev, 0x30, 0x01); //Enable GPIO
+ pnp_write_config(dev, 0x60, 0x0a); //Base addr high
+ pnp_write_config(dev, 0x61, 0x00); //Base addr low
+ // 17 ... 10
+ pnp_write_config(dev, 0xe0, 0x04); //GPIO1 output enable 0000 0100
+ pnp_write_config(dev, 0xe1, 0xff); //GPIO1 output data 1111 1111
+ //0xe2: GPIO1 status (for reading inputs)
+ pnp_write_config(dev, 0xe3, 0x04); //GPIO1 drive enable 0000 0100
+ pnp_write_config(dev, 0xe4, 0x00); //GPIO1 PME enable 0000 0000
+ pnp_write_config(dev, 0xe5, 0x00); //GPIO1 input detect select 0000 0000
+ pnp_write_config(dev, 0xe6, 0x40); //GPIO1 event status 0100 0000
+
+ // 27 ... 20
+ pnp_write_config(dev, 0xd0, 0x00); //GPIO2 output enable 0000 0000
+ pnp_write_config(dev, 0xd1, 0xff); //GPIO2 output data 1111 1111
+ // 0xd2: GPIO2 status (for reading inputs)
+ pnp_write_config(dev, 0xd3, 0x00); //GPIO2 drive enable 0000 0000
+
+ // 37 ... 30
+ pnp_write_config(dev, 0xc0, 0x00); //GPIO3 output enable 0000 0000
+ pnp_write_config(dev, 0xc1, 0xff); //GPIO3 output data 1111 1111
+ // 0xc2: GPIO3 status (for reading inputs)
+
+ // 47 ... 40
+ pnp_write_config(dev, 0xb0, 0x04); //GPIO4 output enable 0000 0100
+ pnp_write_config(dev, 0xb1, 0x04); //GPIO4 output data 0000 0100
+ // 0xb2: GPIO4 status (for reading inputs)
+ pnp_write_config(dev, 0xb3, 0x04); //GPIO4 drive enable 0000 0100
+ pnp_write_config(dev, 0xb4, 0x00); //GPIO4 PME enable 0000 0000
+ pnp_write_config(dev, 0xb5, 0x00); //GPIO4 input detect select 0000 0000
+ pnp_write_config(dev, 0xb6, 0x00); //GPIO4 event status 0000 0000
+
+ // 37-35 & 54-50
+ pnp_write_config(dev, 0xa0, 0x00); //GPIO5 output enable 0000 0000
+ pnp_write_config(dev, 0xa1, 0x1f); //GPIO5 output data 0001 1111
+ // 0xa2: GPIO5 status (for reading inputs)
+ //pnp_write_config(dev, 0xa3, 0x00); //GPIO5 drive enable 0000 0000 (?)
+ pnp_write_config(dev, 0xa4, 0x00); //GPIO5 PME enable 0000 0000
+ pnp_write_config(dev, 0xa5, 0xff); //GPIO5 input detect select 0000 0000
+ pnp_write_config(dev, 0xa6, 0xe0); //GPIO5 event status 0000 0000
+
+ // 67 ... 60
+ pnp_write_config(dev, 0x90, 0x00); //GPIO6 output enable 0000 0000
+ pnp_write_config(dev, 0x91, 0xff); //GPIO6 output data 1111 1111
+ // 0x92: GPIO6 status (for reading inputs)
+ pnp_write_config(dev, 0x93, 0x00); //GPIO6 drive enable 0000 0000
+
+ // 77 ... 70
+ pnp_write_config(dev, 0x80, 0x00); //GPIO7 output enable 0000 0000
+ pnp_write_config(dev, 0x81, 0xff); //GPIO7 output data 1111 1111
+ // 0x82: GPIO7 status (for reading inputs)
+ pnp_write_config(dev, 0x83, 0x00); //GPIO7 drive enable 0000 0000
+
+
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+
static void sbxxx_enable_48mhzout(void)
{
@@ -62,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
u8 byte;
- pci_devfn_t dev;
+ device_t dev;
#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
hudson_pci_port80();
@@ -73,6 +176,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amd_initmmio();
+ post_code(0x29);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* enable SIO LPC decode */
@@ -94,41 +199,50 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* enable SIO clock */
sbxxx_enable_48mhzout();
- ite_kill_watchdog(GPIO_DEV);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- ite_enable_3vsbsw(GPIO_DEV);
+
+ /* Enable serial console */
+ fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
+ /* Initialize GPIO registers */
+ printk(BIOS_DEBUG, "GPIO INIT\n");
+ gpio_init(GPIO_DEV);
+
+ /* Initialize parallel port */
+ printk(BIOS_DEBUG, "PARPORT INIT\n");
+ parport_init(PP_DEV);
+
+ printk(BIOS_DEBUG, "SECONDARY SMBUS\n");
/* turn on secondary smbus at b20 */
outb(0x28, 0xcd6);
byte = inb(0xcd7);
byte |= 1;
outb(byte, 0xcd7);
-
- /* set DDR3 voltage */
- byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
-
- /* default is byte = 0x0, so no need to set it in this case */
- if (byte)
- do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
}
-
/* Halt if there was a built in self test failure */
+ printk(BIOS_DEBUG, "SELFTEST\n");
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x (cpu_init_detectedx: %08lx)\n", val, cpu_init_detectedx);
post_code(0x37);
- agesawrapper_amdinitreset();
+ int s3resume = acpi_is_wakeup_s3();
+ if (s3resume) {
+ printk(BIOS_DEBUG, "is s3resume\n");
+ } else {
+ printk(BIOS_DEBUG, "is cold boot\n");
+ printk(BIOS_SPEW, "agesawrapper_amdinitreset()\n");
+ agesawrapper_amdinitreset();
+ }
post_code(0x39);
-
+ printk(BIOS_SPEW, "agesawrapper_amdinitearly()\n");
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
+ post_code(0x42);
+ s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
+ printk(BIOS_INFO, "Cold boot\n");
post_code(0x40);
agesawrapper_amdinitpost();
post_code(0x41);
@@ -136,18 +250,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
disable_cache_as_ram();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
-
post_code(0x60);
agesawrapper_amdinitresume();
amd_initcpuio();
agesawrapper_amds3laterestore();
-
post_code(0x61);
prepare_for_resume();
}
post_code(0x50);
+ //printk(BIOS_SPEW, "Copy and run...\n");
copy_and_run();
-
post_code(0x54); /* Should never see this post code. */
}
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