[coreboot-gerrit] Patch merged into coreboot/master: intel/sandybridge post-car: Redo MTRR settings and stack selection

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit bfca67078cfddc18994fa6bbe9094a2ecca275a3
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Jul 22 22:48:35 2016 +0300

    intel/sandybridge post-car: Redo MTRR settings and stack selection
    
    Adapt implementation from haswell to prepare for removal of HIGH_MEMORY_SAVE
    and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions
    are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM.
    
    Also fixes regression of slower S3 resume path after commit
       9b99152 intel/sandybridge: Use common ACPI S3 recovery
    
    Skipping low memory backup and using stage cache for ramstage decreases
    time spent on S3 resume path by 50 ms on samsung/lumpy.
    
    Change-Id: I2afee3662e73e8e629188258b2f4119e02d60305
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
    Reviewed-on: https://review.coreboot.org/15790
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)


See https://review.coreboot.org/15790 for details.

-gerrit