[coreboot-gerrit] New patch to review for coreboot: soc/intel/common/lpss_i2c: fix NULL dereference in error path

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17468

-gerrit

commit ee0ac515ed59ba7e8ac66946973bc1571f9b7260
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Nov 18 08:10:35 2016 -0600

    soc/intel/common/lpss_i2c: fix NULL dereference in error path
    
    If the SoC clock speed is not supported there is supposed to
    be an error printed. However, the value printed was wrong which
    was dereferencing a NULL struct. Fix that.
    
    Change-Id: I5021ad8c1581d1935b39875ffa3aa00b594c537a
    Found-by: Coverity Scan #1365977
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/common/lpss_i2c.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c
index 49fb85d..4e779b4 100644
--- a/src/soc/intel/common/lpss_i2c.c
+++ b/src/soc/intel/common/lpss_i2c.c
@@ -539,7 +539,7 @@ static int lpss_i2c_gen_config_rise_fall_time(struct lpss_i2c_regs *regs,
 
 	if (soc == NULL) {
 		printk(BIOS_ERR, "lpss_i2c: invalid SoC clock speed %d MHz\n",
-			soc->clk_speed_mhz);
+			speed);
 		return -1;
 	}