[coreboot-gerrit] Patch set updated for coreboot: fsp2_0: implement stage cache for silicon init
Brandon Breitenstein (brandon.breitenstein@intel.com)
gerrit at coreboot.org
Thu Nov 17 22:17:13 CET 2016
Brandon Breitenstein (brandon.breitenstein at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17460
-gerrit
commit 12864a204a40f73972974acec654586c717c134c
Author: Brandon Breitenstein <brandon.breitenstein at intel.com>
Date: Thu Nov 17 12:23:04 2016 -0800
fsp2_0: implement stage cache for silicon init
Stage cache will save ~20ms on S3 resume for apollolake platforms.
Implementing the cache in ramstage to save silicon init and reload
it on resume. This patch adds passing S3 status to silicon init in
order to verify that the wake is from S3 and not for some other
reason. This patch also includes changes needed for quark and
skylake platforms that require fsp 2.0.
BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for reef and tested boot and S3 resume path saving 20ms
Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6
Signed-off-by: Brandon Breitenstein <brandon.breitenstein at intel.com>
---
src/drivers/intel/fsp2_0/include/fsp/api.h | 2 +-
src/drivers/intel/fsp2_0/silicon_init.c | 18 +++++++++++++++++-
src/soc/intel/apollolake/chip.c | 5 ++++-
src/soc/intel/quark/chip.c | 6 +++++-
src/soc/intel/skylake/chip_fsp20.c | 8 +++++++-
5 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 553fc52..b012040 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -38,7 +38,7 @@ enum fsp_notify_phase {
/* Main FSP stages */
void fsp_memory_init(bool s3wake);
-void fsp_silicon_init(void);
+void fsp_silicon_init(bool s3wake);
/* Callbacks for updating stage-specific parameters */
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd);
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index b911553..39e6b60 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -18,6 +18,7 @@
#include <fsp/api.h>
#include <fsp/util.h>
#include <program_loading.h>
+#include <stage_cache.h>
#include <string.h>
#include <timestamp.h>
@@ -61,7 +62,7 @@ static void do_silicon_init(struct fsp_header *hdr)
}
}
-void fsp_silicon_init(void)
+void fsp_silicon_init(bool s3wake)
{
struct fsp_header *hdr = &fsps_hdr;
struct cbfsf file_desc;
@@ -69,6 +70,17 @@ void fsp_silicon_init(void)
const char *name = CONFIG_FSP_S_CBFS;
void *dest;
size_t size;
+ struct prog fsps = PROG_INIT(PROG_REFCODE, name);
+
+ if (s3wake && !IS_ENABLED(NO_STAGE_CACHE)) {
+ printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n");
+ stage_cache_load_stage(STAGE_REFCODE, &fsps);
+ if (fsp_validate_component(hdr, prog_rdev(&fsps)) != CB_SUCCESS)
+ die("On resume fsps header is invalid\n");
+ do_silicon_init(hdr);
+ return;
+ }
+
if (cbfs_boot_locate(&file_desc, name, NULL)) {
printk(BIOS_ERR, "Could not locate %s in CBFS\n", name);
@@ -98,6 +110,10 @@ void fsp_silicon_init(void)
if (fsp_validate_component(hdr, &rdev) != CB_SUCCESS)
die("Invalid FSPS header!\n");
+ prog_set_area(&fsps, dest, size);
+
+ stage_cache_add(STAGE_REFCODE, &fsps);
+
/* Signal that FSP component has been loaded. */
prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL);
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 12aea77..ef5908c 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -25,6 +25,7 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <romstage_handoff.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/intel/common/vbt.h>
@@ -259,6 +260,7 @@ static void set_power_limits(void)
static void soc_init(void *data)
{
struct global_nvs_t *gnvs;
+ struct romstage_handoff *handoff;
/* Save VBT info and mapping */
vbt = vbt_get(&vbt_rdev);
@@ -267,7 +269,8 @@ static void soc_init(void *data)
* default policy that doesn't honor boards' requirements. */
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
- fsp_silicon_init();
+ handoff = romstage_handoff_find_or_add();
+ fsp_silicon_init(handoff->s3_resume);
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index 77fb1fd..150df12 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -17,6 +17,7 @@
#include <assert.h>
#include <console/console.h>
#include <device/device.h>
+#include <romstage_handoff.h>
#include <soc/ramstage.h>
#include <soc/reg_access.h>
@@ -101,6 +102,8 @@ static const struct reg_script thermal_init_script[] = {
static void chip_init(void *chip_info)
{
+ struct romstage_handoff *handoff;
+
/* Validate the temperature settings */
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255);
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS
@@ -117,7 +120,8 @@ static void chip_init(void *chip_info)
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
/* Perform silicon specific init. */
- fsp_silicon_init();
+ handoff = romstage_handoff_find_or_add();
+ fsp_silicon_init(handoff->s3_resume);
}
static void pci_domain_set_resources(device_t dev)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 49569d9..582cdbf 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -25,6 +25,7 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <romstage_handoff.h>
#include <soc/acpi.h>
#include <soc/interrupt.h>
#include <soc/irq.h>
@@ -34,8 +35,13 @@
void soc_init_pre_device(void *chip_info)
{
+ struct romstage_handoff *handoff;
+
+ /* Get S3 status to pass to silicon init. */
+ handoff = romstage_handoff_find_or_add();
+
/* Perform silicon specific init. */
- fsp_silicon_init();
+ fsp_silicon_init(handoff->s3_resume);
}
static void pci_domain_set_resources(device_t dev)
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