[coreboot-gerrit] New patch to review for coreboot: intel post-car: Increase stacktop alignment

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17461

-gerrit

commit 8771faba107d98a4f3092e6b0de851d85852c1f6
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Nov 17 22:39:29 2016 +0200

    intel post-car: Increase stacktop alignment
    
    Align top of stack to 8 bytes, value documented as FSP1.1 requirement.
    Also fix some cases of uintptr_t casted to unsigned long.
    
    Change-Id: I5bbd100eeb673417da205a2c2c3410fef1af61f0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/haswell/romstage.c           | 4 +---
 src/drivers/intel/fsp1_1/stack.c           | 4 +---
 src/lib/romstage_stack.c                   | 3 +++
 src/soc/intel/baytrail/romstage/romstage.c | 4 +---
 src/soc/intel/broadwell/romstage/stack.c   | 4 +---
 5 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index f823c55..48920b3 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -69,15 +69,13 @@ static inline u32 *stack_push(u32 *stack, u32 value)
  * cache-as-ram is torn down as well as the MTRR settings to use. */
 static void *setup_romstage_stack_after_car(void)
 {
-	uintptr_t top_of_stack;
 	int num_mtrrs;
 	u32 *slot;
 	u32 mtrr_mask_upper;
 	u32 top_of_ram;
 
 	/* Top of stack needs to be aligned to a 4-byte boundary. */
-	top_of_stack = romstage_ram_stack_top() & ~3;
-	slot = (void *)top_of_stack;
+	slot = (void *)romstage_ram_stack_top();
 	num_mtrrs = 0;
 
 	/* The upper bits of the MTRR mask need to set according to the number
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
index 6a64921..059f8ba 100644
--- a/src/drivers/intel/fsp1_1/stack.c
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -35,14 +35,12 @@ void *setup_stack_and_mtrrs(void)
 	uint32_t max_mtrrs;
 	uint32_t num_mtrrs;
 	uint32_t *slot;
-	unsigned long top_of_stack;
 
 	/* Display the MTTRs */
 	soc_display_mtrrs();
 
 	/* Top of stack needs to be aligned to a 8-byte boundary. */
-	top_of_stack = romstage_ram_stack_top();
-	slot = (void *)top_of_stack;
+	slot = (void *)romstage_ram_stack_top();
 	num_mtrrs = 0;
 	max_mtrrs = soc_get_variable_mtrr_count(NULL);
 
diff --git a/src/lib/romstage_stack.c b/src/lib/romstage_stack.c
index fde9d1b..ed6f09b 100644
--- a/src/lib/romstage_stack.c
+++ b/src/lib/romstage_stack.c
@@ -44,5 +44,8 @@ uintptr_t romstage_ram_stack_top(void)
 	uintptr_t stack_top = romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE,
 		ROMSTAGE_STACK_CBMEM);
 	stack_top += ROMSTAGE_RAM_STACK_SIZE;
+
+	/* Make it aligned to a 8-byte boundary. */
+	stack_top = ALIGN_DOWN(stack_top, 8);
 	return stack_top;
 }
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 9cf110e..a61b571 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -261,15 +261,13 @@ static inline uint32_t *stack_push(u32 *stack, u32 value)
  * cache-as-ram is torn down as well as the MTRR settings to use. */
 static void *setup_stack_and_mttrs(void)
 {
-	unsigned long top_of_stack;
 	int num_mtrrs;
 	uint32_t *slot;
 	uint32_t mtrr_mask_upper;
 	uint32_t top_of_ram;
 
 	/* Top of stack needs to be aligned to a 4-byte boundary. */
-	top_of_stack = romstage_ram_stack_top() & ~3;
-	slot = (void *)top_of_stack;
+	slot = (void *)romstage_ram_stack_top();
 	num_mtrrs = 0;
 
 	/* The upper bits of the MTRR mask need to set according to the number
diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c
index 86a1c02..f17cd82 100644
--- a/src/soc/intel/broadwell/romstage/stack.c
+++ b/src/soc/intel/broadwell/romstage/stack.c
@@ -34,15 +34,13 @@ static inline uint32_t *stack_push(u32 *stack, u32 value)
  * cache-as-ram is torn down as well as the MTRR settings to use. */
 void *setup_stack_and_mttrs(void)
 {
-	unsigned long top_of_stack;
 	int num_mtrrs;
 	uint32_t *slot;
 	uint32_t mtrr_mask_upper;
 	uint32_t top_of_ram;
 
 	/* Top of stack needs to be aligned to a 4-byte boundary. */
-	top_of_stack = romstage_ram_stack_top() & ~3;
-	slot = (void *)top_of_stack;
+	slot = (void *)romstage_ram_stack_top();
 	num_mtrrs = 0;
 
 	/* The upper bits of the MTRR mask need to set according to the number