[coreboot-gerrit] Patch merged into coreboot/master: google/snappy: Update DPTF settings

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 676b4878971b2fd782fbf97095d7cf0867ba00fe
Author: Wisley Chen <wisley.chen at quantatw.com>
Date:   Tue Nov 15 03:51:13 2016 -0500

    google/snappy: Update DPTF settings
    
    1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
       CPU passive point:100, critical point:105
       TSR1 passive point:48, critial point:65
       TSR2 passive point:85, critial point:100
    
    2. Update PL1/PL2 Min Power Limit/Max Power Limit
       Set PL1 min to 3W, and max to 6W
       Set PL2 min and max to 8W
    
    3. Change thermal relationship table (TRT) setting.
       The TRT of TCHG is TSR1, but real sensor is TSR2.
    
    BRANCH=master
    BUG=none
    TEST= Compiled, verified by thermal team.
    
    Change-Id: Ib197c36eca88e3d05f632025cf3c238e1a2eae23
    Signed-off-by: Wisley Chen <wisley.chen at quantatw.com>
    Reviewed-on: https://review.coreboot.org/17426
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See https://review.coreboot.org/17426 for details.

-gerrit