[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Enable and Lock AES feature register
Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri@intel.com)
gerrit at coreboot.org
Thu Nov 17 05:21:41 CET 2016
Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17396
-gerrit
commit 34d842b33909c0a47557a46bc4f20c5f6289dc82
Author: Nelson, Cole <colex.nelson at intel.com>
Date: Fri Nov 11 14:17:37 2016 -0800
soc/intel/apollolake: Enable and Lock AES feature register
Configure MPinit feature register during boot and s3 resume.
Enable and Lock Advanced Encryption Standard (AES-NI) feature.
BUG=chrome-os-partner:56922
BRANCH=None
Change-Id: Id16f62ec4e7463a466c43d67f2b03e07e324fa93
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
---
src/soc/intel/apollolake/cpu.c | 6 ++++++
src/soc/intel/apollolake/include/soc/cpu.h | 3 +++
2 files changed, 9 insertions(+)
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index e2d3a9d..916d7c5 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -43,6 +43,12 @@ static const struct reg_script core_msr_script[] = {
REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
/* Disable support for MONITOR and MWAIT instructions */
REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0),
+ /*
+ * Enable and Lock the Advanced Encryption Standard (AES-NI)
+ * feature register
+ */
+ REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK,
+ FEATURE_CONFIG_LOCK),
REG_SCRIPT_END
};
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 66fc29b..38ce4ff 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -66,6 +66,9 @@ void set_max_freq(void);
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
+#define MSR_FEATURE_CONFIG 0x13c
+#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL
+#define FEATURE_CONFIG_LOCK (1 << 0)
#define MSR_POWER_CTL 0x1fc
#define MSR_L2_QOS_MASK(reg) (0xd10 + reg)
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