[coreboot-gerrit] New patch to review for coreboot: src/cpu/intel: Add P4 model F6x

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17410

-gerrit

commit d944b1ebc3de9f193eb85c0beda1284fbaff3704
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Sun Nov 13 18:32:52 2016 +0100

    src/cpu/intel: Add P4 model F6x
    
    Change-Id: I9c691db73e3ec44895f623ede5a7ee04c13e1851
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/cpu/intel/model_f6x/Kconfig          |  8 +++++
 src/cpu/intel/model_f6x/Makefile.inc     |  3 ++
 src/cpu/intel/model_f6x/model_f6x_init.c | 61 ++++++++++++++++++++++++++++++++
 3 files changed, 72 insertions(+)

diff --git a/src/cpu/intel/model_f6x/Kconfig b/src/cpu/intel/model_f6x/Kconfig
new file mode 100644
index 0000000..09f09bd
--- /dev/null
+++ b/src/cpu/intel/model_f6x/Kconfig
@@ -0,0 +1,8 @@
+config CPU_INTEL_MODEL_64X
+	bool
+	select ARCH_BOOTBLOCK_X86_32
+	select ARCH_VERSTAGE_X86_32
+	select ARCH_ROMSTAGE_X86_32
+	select ARCH_RAMSTAGE_X86_32
+	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f6x/Makefile.inc b/src/cpu/intel/model_f6x/Makefile.inc
new file mode 100644
index 0000000..b71f96d
--- /dev/null
+++ b/src/cpu/intel/model_f6x/Makefile.inc
@@ -0,0 +1,3 @@
+ramstage-y += model_f6x_init.c
+
+#cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f6x/microcode.bin
diff --git a/src/cpu/intel/model_f6x/model_f6x_init.c b/src/cpu/intel/model_f6x/model_f6x_init.c
new file mode 100644
index 0000000..c533501
--- /dev/null
+++ b/src/cpu/intel/model_f6x/model_f6x_init.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+
+static void model_f6x_init(struct device *cpu)
+{
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	if (!intel_ht_sibling()) {
+		/* MTRRs are shared between threads */
+		x86_setup_mtrrs();
+		x86_mtrr_check();
+
+		/* Update the microcode */
+		intel_update_microcode_from_cbfs();
+	}
+
+	/* Enable the local CPU APICs */
+	setup_lapic();
+
+	/* Start up my CPU siblings */
+	intel_sibling_init(cpu);
+};
+
+static struct device_operations cpu_dev_ops = {
+	.init = model_f6x_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0f62 },
+	{ X86_VENDOR_INTEL, 0x0f64 },
+	{ X86_VENDOR_INTEL, 0x0f65 },
+	{ X86_VENDOR_INTEL, 0x0f68 },
+	{ 0, 0 },
+};
+
+static const struct cpu_driver model_f6x __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};