[coreboot-gerrit] Patch set updated for coreboot: riscv: change payload() to pass the config string pointer as arg0

[Ronald G. Minnich (rminnich@gmail.com)]

Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17254

-gerrit

commit 73048ab4abb6c548d6702a5a7be47915f115df9e
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Sun Nov 6 16:13:52 2016 -0800

    riscv: change payload() to pass the config string pointer as arg0
    
    The riscv 1.9 standard defines a textual config string to be passed
    to kernels and hypervisors. A pointer to this string is available
    at a platform-dependent location, default 0x100c on all extant platforms.
    
    Define a new config variable, ARCH_CONFIGSTRING_RISCV, to contain
    this location and change payload() arguments so arg0 is this pointer
    and arg1 is the pointer to the payload.
    
    Change-Id: I3be7f1712accf2d726704e4c970f22749d3c3f36
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
 src/arch/riscv/payload.S | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S
index 3261a80..ce88bc3 100644
--- a/src/arch/riscv/payload.S
+++ b/src/arch/riscv/payload.S
@@ -11,10 +11,12 @@
  * GNU General Public License for more details.
  */
 
+// "return" to a payload pointed to by a1 with
+// an M-mode pointer (or, to upper levels, physical address)
+// to the config string in a0.
 	.global riscvpayload
 riscvpayload:
-	/* Jump to a0 in S-mode */
-	mv t0,a0
+	mv t0,a1
 	csrw mepc, t0
 	csrr t0, mstatus
 	li t1, ~(3<<11)