[coreboot-gerrit] Patch merged into coreboot/master: cpu/x86/mtrr: allow temporary MTRR range during coreboot

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 2bebd7bc93e248f5bdf5677d07802eb9e14528b0
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Nov 10 15:15:35 2016 -0600

    cpu/x86/mtrr: allow temporary MTRR range during coreboot
    
    Certain platforms have a poorly performing SPI prefetcher so even if
    accessing MMIO BIOS once the fetch time can be impacted. Payload
    loading is one example where it can be impacted. Therefore, add the
    ability for a platform to reconfigure the currently running CPU's
    variable MTRR settings for the duration of coreboot's execution.
    
    The function mtrr_use_temp_range() is added which uses the previous
    MTRR solution as a basis along with a new range and type to use.
    A new solution is calculated with the updated settings and the
    original solution is put back prior to exiting coreboot into the OS
    or payload.
    
    Using this patch on apollolake reduced depthcharge payload loading
    by 75 ms.
    
    BUG=chrome-os-partner:56656,chrome-os-partner:59682
    
    Change-Id: If87ee6f88e0ab0a463eafa35f89a5f7a7ad0fb85
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/17371
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh <furquan at google.com>
    Reviewed-by: Andrey Petrov <andrey.petrov at intel.com>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See https://review.coreboot.org/17371 for details.

-gerrit