[coreboot-gerrit] New patch to review for coreboot: nb/intel/sandybridge/raminit: Fix CAS Write Latency

[Patrick Rudolph (siro@das-labor.org)]

Patrick Rudolph (siro at das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17389

-gerrit

commit bed826062895e03f037fe14345d5ea7af9998b90
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Fri Nov 11 19:17:56 2016 +0100

    nb/intel/sandybridge/raminit: Fix CAS Write Latency
    
    As documented in DDR3 spec for MR2 the CWL is based on DDR frequency.
    There's no to little difference for most memory modules operating at DDR3-1333.
    
    It might fix problems for memory modules that operate at a higher frequency.
    Memory modules with low CL values should work even better.
    
    Change-Id: Ib90b5de872a219cf80b4976b6dfae6bc02e298f4
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
 src/northbridge/intel/sandybridge/raminit.c | 38 ++++++++++++++++++++---------
 1 file changed, 27 insertions(+), 11 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 46dc7c7..8123014 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -491,17 +491,33 @@ static void dram_find_common_params(ramctr_timing *ctrl)
 		die("No valid DIMMs found");
 }
 
-static u8 get_CWL(u8 CAS)
+/* CAS write latency. To be programmed in MR2.
+ * See DDR3 SPEC for MR2 documentation. */
+static u8 get_CWL(u32 tCK)
 {
-	/* Get CWL based on CAS using the following rule:
-	 *       _________________________________________
-	 * CAS: | 4T | 5T | 6T | 7T | 8T | 9T | 10T | 11T |
-	 * CWL: | 5T | 5T | 5T | 6T | 6T | 7T |  7T |  8T |
-	 */
-	static const u8 cas_cwl_map[] = { 5, 5, 5, 6, 6, 7, 7, 8 };
-	if (CAS > 11)
+	/* Get CWL based on tCK using the following rule: */
+	switch (tCK) {
+	case TCK_1333MHZ:
+		return 12;
+	case TCK_1200MHZ:
+	case TCK_1100MHZ:
+		return 11;
+	case TCK_1066MHZ:
+	case TCK_1000MHZ:
+		return 10;
+	case TCK_933MHZ:
+	case TCK_900MHZ:
+		return 9;
+	case TCK_800MHZ:
+	case TCK_700MHZ:
 		return 8;
-	return cas_cwl_map[CAS - 4];
+	case TCK_666MHZ:
+		return 7;
+	case TCK_533MHZ:
+		return 6;
+	default:
+		return 5;
+	}
 }
 
 /* Frequency multiplier.  */
@@ -713,7 +729,7 @@ static void dram_timing(ramctr_timing * ctrl)
 	val32 = (1000 << 8) / ctrl->tCK;
 	printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32);
 
-	/* Find CAS and CWL latencies */
+	/* Find CAS latency */
 	val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK;
 	printk(BIOS_DEBUG, "Minimum  CAS latency   : %uT\n", val);
 	/* Find lowest supported CAS latency that satisfies the minimum value */
@@ -734,7 +750,7 @@ static void dram_timing(ramctr_timing * ctrl)
 
 	printk(BIOS_DEBUG, "Selected CAS latency   : %uT\n", val);
 	ctrl->CAS = val;
-	ctrl->CWL = get_CWL(ctrl->CAS);
+	ctrl->CWL = get_CWL(ctrl->tCK);
 	printk(BIOS_DEBUG, "Selected CWL latency   : %uT\n", ctrl->CWL);
 
 	/* Find tRCD */