[coreboot-gerrit] Patch set updated for coreboot: util/inteltool: Add modelf6x
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Fri Nov 11 18:35:28 CET 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17385
-gerrit
commit 4f74cba6efdc319adb5060cecbdef101588cb0e7
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Fri Nov 11 18:14:43 2016 +0100
util/inteltool: Add modelf6x
Change-Id: I9514879d425882aa10438956115fb7b79fc69b83
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
util/inteltool/cpu.c | 155 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 155 insertions(+)
diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index afafc63..261ba83 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -731,6 +731,160 @@ int print_intel_core_msrs(void)
};
+
+ /*
+ * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual
+ * September 2016
+ */
+
+ static const msr_entry_t modelf6x_global_msrs[] = {
+ { 0x0000, "IA32_P5_MC_ADDR" },
+ { 0x0001, "IA32_P5_MC_TYPE" },
+ { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
+ { 0x0017, "IA32_PLATFORM_ID" },
+ { 0x002a, "MSR_EBC_HARD_POWERON" },
+ { 0x002b, "MSR_EBC_SOFT_POWERON" },
+ { 0x002c, "MSR_EBC_FREQUENCY_ID" },
+// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
+ { 0x017b, "IA32_MCG_CTL" },
+
+ { 0x019c, "IA32_THERM_STATUS" },
+ { 0x019d, "MSR_THERM2_CTL" },
+ { 0x01a0, "IA32_MISC_ENABLE" },
+ { 0x01a1, "MSR_PLATFORM_BRV" },
+ { 0x0200, "IA32_MTRR_PHYSBASE0" },
+ { 0x0201, "IA32_MTRR_PHYSMASK0" },
+ { 0x0202, "IA32_MTRR_PHYSBASE1" },
+ { 0x0203, "IA32_MTRR_PHYSMASK1" },
+ { 0x0204, "IA32_MTRR_PHYSBASE2" },
+ { 0x0205, "IA32_MTRR_PHYSMASK2" },
+ { 0x0206, "IA32_MTRR_PHYSBASE3" },
+ { 0x0207, "IA32_MTRR_PHYSMASK3" },
+ { 0x0208, "IA32_MTRR_PHYSBASE4" },
+ { 0x0209, "IA32_MTRR_PHYSMASK4" },
+ { 0x020a, "IA32_MTRR_PHYSBASE5" },
+ { 0x020b, "IA32_MTRR_PHYSMASK5" },
+ { 0x020c, "IA32_MTRR_PHYSBASE6" },
+ { 0x020d, "IA32_MTRR_PHYSMASK6" },
+ { 0x020e, "IA32_MTRR_PHYSBASE7" },
+ { 0x020f, "IA32_MTRR_PHYSMASK7" },
+ { 0x0250, "IA32_MTRR_FIX64K_00000" },
+ { 0x0258, "IA32_MTRR_FIX16K_80000" },
+ { 0x0259, "IA32_MTRR_FIX16K_A0000" },
+ { 0x0268, "IA32_MTRR_FIX4K_C0000" },
+ { 0x0269, "IA32_MTRR_FIX4K_C8000" },
+ { 0x026a, "IA32_MTRR_FIX4K_D0000" },
+ { 0x026b, "IA32_MTRR_FIX4K_D8000" },
+ { 0x026c, "IA32_MTRR_FIX4K_E0000" },
+ { 0x026d, "IA32_MTRR_FIX4K_E8000" },
+ { 0x026e, "IA32_MTRR_FIX4K_F0000" },
+ { 0x026f, "IA32_MTRR_FIX4K_F8000" },
+ { 0x02ff, "IA32_MTRR_DEF_TYPE" },
+ { 0x0300, "MSR_BPU_COUNTER0" },
+ { 0x0301, "MSR_BPU_COUNTER1" },
+ { 0x0302, "MSR_BPU_COUNTER2" },
+ { 0x0303, "MSR_BPU_COUNTER3" },
+
+ { 0x400, "IA32_MC0_CTL" },
+ { 0x401, "IA32_MC0_STATUS" },
+ { 0x402, "IA32_MC0_ADDR" },
+ { 0x403, "IA32_MC0_MISC" },
+ { 0x404, "IA32_MC1_CTL" },
+ { 0x405, "IA32_MC1_STATUS" },
+ { 0x406, "IA32_MC1_ADDR" },
+ { 0x407, "IA32_MC1_MISC" },
+ { 0x408, "IA32_MC2_CTL" },
+ { 0x409, "IA32_MC2_STATUS" },
+ { 0x40a, "IA32_MC2_ADDR" },
+ { 0x40b, "IA32_MC2_MISC" },
+ { 0x40c, "IA32_MC3_CTL" },
+ { 0x40d, "IA32_MC3_STATUS" },
+ { 0x40e, "IA32_MC3_ADDR" },
+ { 0x40f, "IA32_MC3_MISC" },
+ { 0x410, "IA32_MC4_CTL" },
+ { 0x411, "IA32_MC4_STATUS" },
+ { 0x412, "IA32_MC4_ADDR" },
+ { 0x413, "IA32_MC4_MISC" },
+ };
+
+ static const msr_entry_t modelf6x_per_core_msrs[] = {
+ { 0x0010, "IA32_TIME_STAMP_COUNTER" },
+ { 0x001b, "IA32_APIC_BASE" },
+ { 0x003a, "IA32_FEATURE_CONTROL" },
+ { 0x008b, "IA32_BIOS_SIGN_ID" },
+ { 0x009b, "IA32_SMM_MONITOR_CTL" },
+ { 0x00fe, "IA32_MTRRCAP" },
+ { 0x0174, "IA32_SYSENTER_CS" },
+ { 0x0175, "IA32_SYSENTER_ESP" },
+ { 0x0176, "IA32_SYSENTER_EIP" },
+ { 0x0179, "IA32_MCG_CAP" },
+ { 0x017a, "IA32_MCG_STATUS" },
+ { 0x019a, "IA32_CLOCK_MODULATION" },
+ { 0x019b, "IA32_THERM_INTERRUPT" },
+ { 0x01d7, "MSR_LER_FROM_LIP" },
+ { 0x01d8, "MSR_LER_TO_LIP" },
+ { 0x01d9, "MSR_DEBUGCTLA" },
+ { 0x01da, "MSR_LASTBRANCH_TOS" },
+ { 0x01db, "MSR_LASTBRANCH_0" },
+ { 0x01dd, "MSR_LASTBRANCH_2" },
+ { 0x01de, "MSR_LASTBRANCH_3" },
+ { 0x0277, "IA32_PAT" },
+ { 0x0480, "IA32_VMX_BASIC" },
+ { 0x0481, "IA32_VMX_PINBASED_CTLS" },
+ { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
+ { 0x0483, "IA32_VMX_EXIT_CTLS" },
+ { 0x0484, "IA32_VMX_ENTRY_CTLS" },
+ { 0x0485, "IA32_VMX_MISC" },
+ { 0x0486, "IA32_VMX_CR0_FIXED0" },
+ { 0x0487, "IA32_VMX_CR0_FIXED1" },
+ { 0x0488, "IA32_VMX_CR4_FIXED0" },
+ { 0x0489, "IA32_VMX_CR4_FIXED1" },
+ { 0x048a, "IA32_VMX_VMCS_ENUM" },
+ { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
+ { 0x0600, "IA32_DS_AREA" },
+ { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" },
+ { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" },
+ { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" },
+ { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" },
+ { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" },
+ { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" },
+ { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" },
+ { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" },
+ { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" },
+ { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" },
+ { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" },
+ { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" },
+ { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" },
+ { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" },
+ { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" },
+ { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" },
+ { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" },
+ { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" },
+ { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" },
+ { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" },
+ { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" },
+ { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" },
+ { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" },
+ { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" },
+ { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" },
+ { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" },
+ { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" },
+ { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" },
+ { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" },
+ { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" },
+ { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" },
+ { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" },
+ /* Intel Xeon processor 7100 with L3 */
+ { 0x107CC, "MSR_EMON_L3_CTR_CTL0" },
+ { 0x107CD, "MSR_EMON_L3_CTR_CTL1" },
+ { 0x107CE, "MSR_EMON_L3_CTR_CTL2" },
+ { 0x107CF, "MSR_EMON_L3_CTR_CTL3" },
+ { 0x107D0, "MSR_EMON_L3_CTR_CTL4" },
+ { 0x107D1, "MSR_EMON_L3_CTR_CTL5" },
+ { 0x107D2, "MSR_EMON_L3_CTR_CTL6" },
+ { 0x107D3, "MSR_EMON_L3_CTR_CTL7" },
+ };
+
/* Atom N455
*
* This should apply to the following processors:
@@ -1179,6 +1333,7 @@ int print_intel_core_msrs(void)
{ 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
{ 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) },
{ 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
+ { 0x00f60, modelf6x_global_msrs, ARRAY_SIZE(modelf6x_global_msrs), modelf6x_per_core_msrs, ARRAY_SIZE(modelf6x_per_core_msrs) },
{ 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) },
{ 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) },
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