[coreboot-gerrit] New patch to review for coreboot: rockchip/rk3399: Change 933 DPLL to low jitter rate

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17379

-gerrit

commit a0f0863d7881229c862210509f2f229242f70305
Author: Derek Basehore <dbasehore at chromium.org>
Date:   Thu Oct 27 13:51:49 2016 -0700

    rockchip/rk3399: Change 933 DPLL to low jitter rate
    
    This changes the 933 DPLL rate to 928 which has low jitter.
    
    BRANCH=none
    BUG=chrome-os-partner:57845
    TEST=boot kevin and run
    while true; do sleep 0.1; memtester 500K 1 > /dev/null; done
    for several hours
    
    Change-Id: I4d2a8871aaabe3b0a1a165c788af265c5f9e892c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 54ebf8763bb8193c4b36a5e86f0c625b176d31a6
    Original-Change-Id: Iaa12bf67527b6d0e809657c513b8d1c66af25174
    Original-Signed-off-by: Derek Basehore <dbasehore at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/404550
    Original-Reviewed-by: Douglas Anderson <dianders at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/soc/rockchip/rk3399/clock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index e5e3aa1..7754d54 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -558,7 +558,7 @@ void rkclk_configure_ddr(unsigned int hz)
 		break;
 	case 933*MHz:
 		dpll_cfg = (struct pll_div)
-		{.refdiv = 3, .fbdiv = 350, .postdiv1 = 3, .postdiv2 = 1};
+		{.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
 		break;
 	default:
 		die("Unsupported SDRAM frequency, add to clock.c!");