[coreboot-gerrit] New patch to review for coreboot: intel/kblrvp: Enable TPM

[Naresh Solanki (naresh.solanki@intel.com)]

Naresh Solanki (naresh.solanki at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17367

-gerrit

commit dccbcf0de2903b9d70cadc2276212a68f949e774
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date:   Thu Nov 10 22:20:14 2016 +0530

    intel/kblrvp: Enable TPM
    
    Add choice to build without TPM, TPM 1.2 support or TPM 2.0 support.
    
    Additionally configure lpc clock pad used with LPC TPM & update devicetree.cb.
    
    Change-Id: I1c24fdefa6e73637b3037ecf118559abe5fde300
    Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
 src/mainboard/intel/kblrvp/Kconfig            | 23 +++++++++++++++++++++++
 src/mainboard/intel/kblrvp/acpi/mainboard.asl |  2 ++
 src/mainboard/intel/kblrvp/devicetree.cb      |  6 +++++-
 src/mainboard/intel/kblrvp/gpio.h             |  2 +-
 4 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index 7e27d89..ab3c68f 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -17,6 +17,29 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 config CHROMEOS
 	select LID_SWITCH
 
+choice USE_TPM
+	prompt "TPM to USE"
+	default KBLRVP_TPM1_2
+	help
+	  This option allows you to select the TPM to use.
+	  Select whether the board does not have TPM, LPC TPM 1.1 or TPM 2.0
+
+config KBLRVP_NO_TPM
+	bool "TPM is not mounted?"
+	select VBOOT_MOCK_SECDATA if VBOOT
+
+config KBLRVP_TPM1_2
+	bool "LPC TPM 1.1"
+	select MAINBOARD_HAS_LPC_TPM
+
+config KBLRVP_TPM2_0
+	bool "SPI TPM 2.0"
+	select TPM2
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_HAS_LPC_TPM
+
+endchoice
+
 config DRIVERS_GENERIC_MAX98357A
 	default y
 
diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
index 5d2b307..c3234af 100644
--- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl
+++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
@@ -42,5 +42,7 @@ Scope (\_SB)
  */
 Scope (\_SB.PCI0.LPCB)
 {
+#if !IS_ENABLED(CONFIG_KBLRVP_NO_TPM)
 	#include <drivers/pc80/tpm/acpi/tpm.asl>
+#endif
 }
diff --git a/src/mainboard/intel/kblrvp/devicetree.cb b/src/mainboard/intel/kblrvp/devicetree.cb
index 104a454..11d5062 100644
--- a/src/mainboard/intel/kblrvp/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/devicetree.cb
@@ -247,7 +247,11 @@ chip soc/intel/skylake
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO
 		device pci 1e.6 on  end # SDCard
-		device pci 1f.0 on  end # LPC Interface
+		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end # LPC Interface
 		device pci 1f.1 on  end # P2SB
 		device pci 1f.2 on  end # Power Management Controller
 		device pci 1f.3 on  end # Intel HDA
diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/gpio.h
index 5e251d8..83c803f 100644
--- a/src/mainboard/intel/kblrvp/gpio.h
+++ b/src/mainboard/intel/kblrvp/gpio.h
@@ -40,7 +40,7 @@ static const struct pad_config gpio_table[] = {
 /* PM_SLP_S0ix_N */	PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),
 /* LPC_CLKRUN */	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 /* LPC_CLK */		PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),
-/* PCH_LPC_CLK */	PAD_CFG_NC(GPP_A10),
+/* PCH_LPC_CLK */	PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
 /* EC_HID_INT */	PAD_CFG_NC(GPP_A11),
 /* ISH_KB_PROX_INT */	PAD_CFG_NC(GPP_A12),
 /* PCH_SUSPWRACB */	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),