[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: Enable caching of MMIO-mapped BIOS on SPI

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17365

-gerrit

commit 174f86b8a602cab663704cdd50ca43c9145ef4c4
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Thu Nov 10 09:55:23 2016 -0800

    soc/intel/apollolake: Enable caching of MMIO-mapped BIOS on SPI
    
    Commit 4337020b950454815204eed4e43a894be0b125ca removed addition of
    generic ROM caching MTRRs. Unfortunately on Apollolake uncached BIOS
    reads are slow. update_mrc_cache() however takes almost 40ms to read
    256KiB flash block. Explicitly add ROM region as reserved resource
    so that MTRR allocator caches it.
    
    Change-Id: Id41c4f9dd0b691a54178ace1cb92b2802b86860e
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/northbridge.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c
index cc097ba..953b9e5 100644
--- a/src/soc/intel/apollolake/northbridge.c
+++ b/src/soc/intel/apollolake/northbridge.c
@@ -125,7 +125,12 @@ static int mc_add_dram_resources(device_t dev, int index)
 	mmio_resource(dev, index++, bgsm / KiB, (bdsm - bgsm) / KiB);
 
 	/* BDSM -> TOLUD */
-	mmio_resource(dev, index++, bdsm / KiB, (tolud - bdsm) / KiB);
+	reserved_ram_resource(dev, index++, bdsm / KiB, (tolud - bdsm) / KiB);
+
+	/* Memory-mapped BIOS */
+	reserved_ram_resource(dev, index++, -CONFIG_ROM_SIZE / KiB,
+				    CONFIG_ROM_SIZE / KiB);
+
 
 	/* 4G -> TOUUD */
 	base_k = 4ULL*GiB / KiB;