[coreboot-gerrit] Patch set updated for coreboot: intel cache-as-ram: Simplify code [NOTFORMERGE]

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15795

-gerrit

commit e14184618999436619e83d8de967305c1e8be996
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Jul 22 00:04:35 2016 +0300

    intel cache-as-ram: Simplify code [NOTFORMERGE]
    
    No need to toggle CR0 cache disable bit while all MTRRs are
    disabled.
    
    Change-Id: Ie9f4769a4fa5bb6bd3fe0512914905c2ad6d052f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/car/cache_as_ram_ht.inc      | 14 --------------
 src/cpu/intel/haswell/cache_as_ram.inc     | 14 --------------
 src/cpu/intel/model_2065x/cache_as_ram.inc | 14 --------------
 src/cpu/intel/model_206ax/cache_as_ram.inc | 14 --------------
 src/cpu/intel/model_6ex/cache_as_ram.inc   | 14 --------------
 5 files changed, 70 deletions(-)

diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 0252041..0b5e292 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -361,20 +361,6 @@ before_romstage:
 
 	invd
 
-	post_code(0x33)
-
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
-	movl	%eax, %cr0
-
-	post_code(0x36)
-
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$CR0_CacheDisable, %eax
-	movl	%eax, %cr0
-
 	post_code(0x38)
 
 #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index f0d4939..56ee7be 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -209,20 +209,6 @@ before_romstage:
 	andl    $~1, %eax
 	wrmsr
 
-	post_code(0x33)
-
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
-	movl	%eax, %cr0
-
-	post_code(0x36)
-
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$CR0_CacheDisable, %eax
-	movl	%eax, %cr0
-
 	post_code(0x38)
 
 	/* Get number of MTRRs. */
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index 1c7cbed..2523e93 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -204,20 +204,6 @@ before_romstage:
 	andl    $~1, %eax
 	wrmsr
 
-	post_code(0x33)
-
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
-	movl	%eax, %cr0
-
-	post_code(0x36)
-
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$CR0_CacheDisable, %eax
-	movl	%eax, %cr0
-
 	post_code(0x38)
 
 	/* Get number of MTRRs. */
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index f0d4939..56ee7be 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -209,20 +209,6 @@ before_romstage:
 	andl    $~1, %eax
 	wrmsr
 
-	post_code(0x33)
-
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
-	movl	%eax, %cr0
-
-	post_code(0x36)
-
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$CR0_CacheDisable, %eax
-	movl	%eax, %cr0
-
 	post_code(0x38)
 
 	/* Get number of MTRRs. */
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 18e6d5d..ea07221 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -162,20 +162,6 @@ before_romstage:
 
 	invd
 
-	post_code(0x33)
-
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
-	movl	%eax, %cr0
-
-	post_code(0x36)
-
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$CR0_CacheDisable, %eax
-	movl	%eax, %cr0
-
 	post_code(0x38)
 
 #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)