[coreboot-gerrit] Patch set updated for coreboot: intel i945 gm45 x4x post-car: Redo MTRR settings and stack selection
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Thu Nov 10 15:59:36 CET 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15791
-gerrit
commit 77d41fcb567cf639443899a2fd0a21da59ac54c3
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Fri Jul 22 22:53:19 2016 +0300
intel i945 gm45 x4x post-car: Redo MTRR settings and stack selection
Adapt implementation from haswell to prepare for removal of HIGH_MEMORY_SAVE
and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions
are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM.
Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/car/cache_as_ram_ht.inc | 37 ++++++++++++--
src/cpu/intel/model_6ex/cache_as_ram.inc | 37 ++++++++++++--
src/mainboard/lenovo/t400/romstage.c | 1 -
src/mainboard/lenovo/x200/romstage.c | 1 -
src/mainboard/roda/rk9/romstage.c | 1 -
src/northbridge/intel/gm45/Kconfig | 1 +
src/northbridge/intel/gm45/ram_calc.c | 84 +++++++++++++++++++++++++++++++-
src/northbridge/intel/i945/Kconfig | 1 +
src/northbridge/intel/i945/early_init.c | 1 -
src/northbridge/intel/i945/ram_calc.c | 83 ++++++++++++++++++++++++++++++-
src/northbridge/intel/x4x/Kconfig | 1 +
src/northbridge/intel/x4x/ram_calc.c | 83 ++++++++++++++++++++++++++++++-
12 files changed, 318 insertions(+), 13 deletions(-)
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 210d356..0252041 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -337,10 +337,9 @@ before_romstage:
post_code(0x2f)
/* Call romstage.c main function. */
call romstage_main
-
/* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down.
- */
+ * after cache-as-ram is torn down. It also contains the information
+ * for setting up MTRRs. */
movl %eax, %esp
post_code(0x30)
@@ -378,6 +377,8 @@ before_romstage:
post_code(0x38)
+#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+
/* Enable Write Back and Speculative Reads for low RAM. */
movl $MTRR_PHYS_BASE(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
@@ -400,6 +401,36 @@ before_romstage:
wrmsr
#endif
+#else
+
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+1:
+ testl %ebx, %ebx
+ jz 1f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
+ wrmsr
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
+ wrmsr
+ inc %ecx
+
+ dec %ebx
+ jmp 1b
+1:
+
+#endif /* CONFIG_LATE_CBMEM_INIT */
+
post_code(0x39)
/* And enable cache again after setting MTRRs. */
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 1673242..18e6d5d 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -138,10 +138,9 @@ before_romstage:
post_code(0x29)
/* Call romstage.c main function. */
call romstage_main
-
/* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down.
- */
+ * after cache-as-ram is torn down. It also contains the information
+ * for setting up MTRRs. */
movl %eax, %esp
post_code(0x30)
@@ -179,6 +178,8 @@ before_romstage:
post_code(0x38)
+#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+
/* Enable Write Back and Speculative Reads for low RAM. */
movl $MTRR_PHYS_BASE(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
@@ -201,6 +202,36 @@ before_romstage:
wrmsr
#endif
+#else
+
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+1:
+ testl %ebx, %ebx
+ jz 1f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
+ wrmsr
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
+ wrmsr
+ inc %ecx
+
+ dec %ebx
+ jmp 1b
+1:
+
+#endif /* CONFIG_LATE_CBMEM_INIT */
+
post_code(0x39)
/* And enable cache again after setting MTRRs. */
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index bba53d1..821b87f 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -161,7 +161,6 @@ void mainboard_romstage_entry(unsigned long bist)
* this is not a resume. In that case we just create the cbmem toc.
*/
if (s3resume && cbmem_initted) {
- acpi_prepare_for_resume();
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index c1e193a..8c97ae1 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -162,7 +162,6 @@ void mainboard_romstage_entry(unsigned long bist)
* this is not a resume. In that case we just create the cbmem toc.
*/
if (s3resume && cbmem_initted) {
- acpi_prepare_for_resume();
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index df749b9..b7ef1bb 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -192,7 +192,6 @@ void mainboard_romstage_entry(unsigned long bist)
* this is not a resume. In that case we just create the cbmem toc.
*/
if (s3resume && cbmem_initted) {
- acpi_prepare_for_resume();
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 6ee6558..fc53839 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -26,6 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select VGA
select INTEL_EDID
select INTEL_GMA_ACPI
+ select RELOCATABLE_RAMSTAGE
config CBFS_SIZE
hex
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 92f1a7f..4cbf1ee 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -18,13 +18,17 @@
#define __SIMPLE_DEVICE__
#include <stdint.h>
+#include <arch/cpu.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
+#include <cpu/x86/mtrr.h>
#include <cbmem.h>
+#include <program_loading.h>
#include "gm45.h"
+
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
u32 decode_igd_memory_size(const u32 gms)
{
@@ -107,7 +111,85 @@ void *cbmem_top(void)
return (void *) smm_region_start();
}
+static inline u32 *stack_push(u32 *stack, u32 value)
+{
+ stack = &stack[-1];
+ *stack = value;
+ return stack;
+}
+
+/* setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
void *setup_stack_and_mtrrs(void)
{
- return (void*)CONFIG_RAMTOP;
+ uintptr_t top_of_stack;
+ int num_mtrrs;
+ u32 *slot;
+ u32 mtrr_mask_upper;
+ u32 top_of_ram;
+
+ /* Top of stack needs to be aligned to a 4-byte boundary. */
+ top_of_stack = romstage_ram_stack_top() & ~3;
+ slot = (void *)top_of_stack;
+ num_mtrrs = 0;
+
+ /* The upper bits of the MTRR mask need to set according to the number
+ * of physical address bits. */
+ mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1;
+
+ /* The order for each MTRR is value then base with upper 32-bits of
+ * each value coming before the lower 32-bits. The reasoning for
+ * this ordering is to create a stack layout like the following:
+ * +0: Number of MTRRs
+ * +4: MTRR base 0 31:0
+ * +8: MTRR base 0 63:32
+ * +12: MTRR mask 0 31:0
+ * +16: MTRR mask 0 63:32
+ * +20: MTRR base 1 31:0
+ * +24: MTRR base 1 63:32
+ * +28: MTRR mask 1 31:0
+ * +32: MTRR mask 1 63:32
+ */
+
+ /* Cache the ROM as WP just below 4GiB. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
+ num_mtrrs++;
+
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ top_of_ram = (uint32_t)cbmem_top();
+ /* Cache 8MiB below the top of ram. On haswell systems the top of
+ * ram under 4GiB is the start of the TSEG region. It is required to
+ * be 8MiB aligned. Set this area as cacheable so it can be used later
+ * for ramstage before setting up the entire RAM as cacheable. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ /* Cache 8MiB at the top of ram. Top of ram on haswell systems
+ * is where the TSEG region resides. However, it is not restricted
+ * to SMM mode until SMM has been relocated. By setting the region
+ * to cacheable it provides faster access when relocating the SMM
+ * handler as well as using the TSEG region for other purposes. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ /* Save the number of MTRRs to setup. Return the stack location
+ * pointing to the number of MTRRs. */
+ slot = stack_push(slot, num_mtrrs);
+
+ return slot;
}
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index e68a01a..312eb86 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -26,6 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select LAPIC_MONOTONIC_TIMER
select VGA
select INTEL_GMA_ACPI
+ select RELOCATABLE_RAMSTAGE
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 8c41cb8..9523333 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -905,7 +905,6 @@ static void i945_prepare_resume(int s3resume)
* this is not a resume. In that case we just create the cbmem toc.
*/
if (s3resume && cbmem_was_initted) {
- acpi_prepare_for_resume();
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 39ede5f..f37ba83 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -17,10 +17,13 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <arch/cpu.h>
#include <cbmem.h>
#include "i945.h"
#include <console/console.h>
#include <cpu/intel/romstage.h>
+#include <cpu/x86/mtrr.h>
+#include <program_loading.h>
static uintptr_t smm_region_start(void)
{
@@ -71,7 +74,85 @@ u32 decode_igd_memory_size(const u32 gms)
return ggc2uma[gms] << 10;
}
+static inline u32 *stack_push(u32 *stack, u32 value)
+{
+ stack = &stack[-1];
+ *stack = value;
+ return stack;
+}
+
+/* setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
void *setup_stack_and_mtrrs(void)
{
- return (void*)CONFIG_RAMTOP;
+ uintptr_t top_of_stack;
+ int num_mtrrs;
+ u32 *slot;
+ u32 mtrr_mask_upper;
+ u32 top_of_ram;
+
+ /* Top of stack needs to be aligned to a 4-byte boundary. */
+ top_of_stack = romstage_ram_stack_top() & ~3;
+ slot = (void *)top_of_stack;
+ num_mtrrs = 0;
+
+ /* The upper bits of the MTRR mask need to set according to the number
+ * of physical address bits. */
+ mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1;
+
+ /* The order for each MTRR is value then base with upper 32-bits of
+ * each value coming before the lower 32-bits. The reasoning for
+ * this ordering is to create a stack layout like the following:
+ * +0: Number of MTRRs
+ * +4: MTRR base 0 31:0
+ * +8: MTRR base 0 63:32
+ * +12: MTRR mask 0 31:0
+ * +16: MTRR mask 0 63:32
+ * +20: MTRR base 1 31:0
+ * +24: MTRR base 1 63:32
+ * +28: MTRR mask 1 31:0
+ * +32: MTRR mask 1 63:32
+ */
+
+ /* Cache the ROM as WP just below 4GiB. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
+ num_mtrrs++;
+
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ top_of_ram = (uint32_t)cbmem_top();
+ /* Cache 8MiB below the top of ram. On haswell systems the top of
+ * ram under 4GiB is the start of the TSEG region. It is required to
+ * be 8MiB aligned. Set this area as cacheable so it can be used later
+ * for ramstage before setting up the entire RAM as cacheable. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ /* Cache 8MiB at the top of ram. Top of ram on haswell systems
+ * is where the TSEG region resides. However, it is not restricted
+ * to SMM mode until SMM has been relocated. By setting the region
+ * to cacheable it provides faster access when relocating the SMM
+ * handler as well as using the TSEG region for other purposes. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ /* Save the number of MTRRs to setup. Return the stack location
+ * pointing to the number of MTRRs. */
+ slot = stack_push(slot, num_mtrrs);
+
+ return slot;
}
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 4ee90a4..f11a6a9 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -27,6 +27,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select VGA
select INTEL_GMA_ACPI
select EARLY_CBMEM_INIT
+ select RELOCATABLE_RAMSTAGE
config CBFS_SIZE
hex
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 09eec47..1346878 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -20,11 +20,14 @@
#include <cbmem.h>
#include <commonlib/helpers.h>
#include <stdint.h>
+#include <arch/cpu.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
+#include <cpu/x86/mtrr.h>
#include <northbridge/intel/x4x/x4x.h>
+#include <program_loading.h>
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
u32 decode_igd_memory_size(const u32 gms)
@@ -95,7 +98,85 @@ void *cbmem_top(void)
return (void*)(ramtop);
}
+static inline u32 *stack_push(u32 *stack, u32 value)
+{
+ stack = &stack[-1];
+ *stack = value;
+ return stack;
+}
+
+/* setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
void *setup_stack_and_mtrrs(void)
{
- return (void*)CONFIG_RAMTOP;
+ uintptr_t top_of_stack;
+ int num_mtrrs;
+ u32 *slot;
+ u32 mtrr_mask_upper;
+ u32 top_of_ram;
+
+ /* Top of stack needs to be aligned to a 4-byte boundary. */
+ top_of_stack = romstage_ram_stack_top() & ~3;
+ slot = (void *)top_of_stack;
+ num_mtrrs = 0;
+
+ /* The upper bits of the MTRR mask need to set according to the number
+ * of physical address bits. */
+ mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1;
+
+ /* The order for each MTRR is value then base with upper 32-bits of
+ * each value coming before the lower 32-bits. The reasoning for
+ * this ordering is to create a stack layout like the following:
+ * +0: Number of MTRRs
+ * +4: MTRR base 0 31:0
+ * +8: MTRR base 0 63:32
+ * +12: MTRR mask 0 31:0
+ * +16: MTRR mask 0 63:32
+ * +20: MTRR base 1 31:0
+ * +24: MTRR base 1 63:32
+ * +28: MTRR mask 1 31:0
+ * +32: MTRR mask 1 63:32
+ */
+
+ /* Cache the ROM as WP just below 4GiB. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
+ num_mtrrs++;
+
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ top_of_ram = (uint32_t)cbmem_top();
+ /* Cache 8MiB below the top of ram. On haswell systems the top of
+ * ram under 4GiB is the start of the TSEG region. It is required to
+ * be 8MiB aligned. Set this area as cacheable so it can be used later
+ * for ramstage before setting up the entire RAM as cacheable. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ /* Cache 8MiB at the top of ram. Top of ram on haswell systems
+ * is where the TSEG region resides. However, it is not restricted
+ * to SMM mode until SMM has been relocated. By setting the region
+ * to cacheable it provides faster access when relocating the SMM
+ * handler as well as using the TSEG region for other purposes. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ /* Save the number of MTRRs to setup. Return the stack location
+ * pointing to the number of MTRRs. */
+ slot = stack_push(slot, num_mtrrs);
+
+ return slot;
}
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