[coreboot-gerrit] Patch set updated for coreboot: intel: Fix S3 handoff state to ramstage
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Thu Nov 10 15:59:30 CET 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/8172
-gerrit
commit bb599176119e7daad8b6fb52ac0220c9a9e23306
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sat Jun 25 11:40:00 2016 +0300
intel: Fix S3 handoff state to ramstage
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag.
Change-Id: I0f074bb80f06f6f0ddf4212cd8872e94ae57f949
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/lenovo/t400/romstage.c | 22 ++++++++--------------
src/mainboard/lenovo/t60/mainboard.c | 7 +++----
src/mainboard/lenovo/x200/romstage.c | 22 ++++++++--------------
src/mainboard/lenovo/x201/mainboard.c | 5 ++---
src/mainboard/lenovo/x201/romstage.c | 20 ++++++++------------
src/mainboard/lenovo/x60/mainboard.c | 7 +++----
src/mainboard/packardbell/ms2290/romstage.c | 20 +++++++-------------
src/mainboard/roda/rk9/romstage.c | 22 ++++++++--------------
src/northbridge/intel/gm45/northbridge.c | 17 -----------------
src/northbridge/intel/i945/early_init.c | 20 +++++++++++---------
src/northbridge/intel/i945/northbridge.c | 23 -----------------------
src/northbridge/intel/nehalem/nehalem.h | 4 ----
src/northbridge/intel/nehalem/northbridge.c | 21 ---------------------
src/northbridge/intel/sandybridge/early_init.c | 21 ++++++++-------------
src/northbridge/intel/sandybridge/northbridge.c | 21 ---------------------
src/southbridge/intel/i82801gx/i82801gx.h | 2 --
src/southbridge/intel/i82801gx/smi.c | 13 ++-----------
src/southbridge/intel/i82801ix/i82801ix.h | 4 ----
src/southbridge/intel/i82801ix/smi.c | 13 ++-----------
19 files changed, 70 insertions(+), 214 deletions(-)
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 821b87f..546bc77 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -27,6 +27,7 @@
#include <cbmem.h>
#include <lib.h>
#include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
#include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
@@ -55,6 +56,7 @@ void mainboard_romstage_entry(unsigned long bist)
int s3resume = 0;
int cbmem_initted;
u16 reg16;
+ struct romstage_handoff *handoff;
/* basic northbridge setup, including MMCONF BAR */
gm45_early_init();
@@ -156,18 +158,10 @@ void mainboard_romstage_entry(unsigned long bist)
outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38);
cbmem_initted = !cbmem_recovery(s3resume);
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume && cbmem_initted) {
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
- } else {
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC);
- }
-#endif
- printk(BIOS_SPEW, "exit main()\n");
+
+ handoff = romstage_handoff_find_or_add();
+ if (handoff != NULL)
+ handoff->s3_resume = s3resume;
+ else
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
}
diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c
index 44fa402..d8256d2 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -17,12 +17,12 @@
#include <console/console.h>
#include <device/device.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <delay.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#include <arch/io.h>
#include <ec/lenovo/pmh7/pmh7.h>
#include <ec/acpi/ec.h>
#include <ec/lenovo/h8/h8.h>
@@ -49,13 +49,12 @@ int get_cst_entries(acpi_cstate_t **entries)
static void mainboard_init(device_t dev)
{
struct southbridge_intel_i82801gx_config *config;
- device_t dev0, idedev;
+ device_t idedev;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3);
/* If we're resuming from suspend, blink suspend LED */
- dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
- if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
+ if (acpi_is_wakeup_s3())
ec_write(0x0c, 0xc7);
idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index 8c97ae1..6af4dea 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -27,6 +27,7 @@
#include <cbmem.h>
#include <lib.h>
#include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
#include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
@@ -56,6 +57,7 @@ void mainboard_romstage_entry(unsigned long bist)
int s3resume = 0;
int cbmem_initted;
u16 reg16;
+ struct romstage_handoff *handoff;
/* basic northbridge setup, including MMCONF BAR */
gm45_early_init();
@@ -157,18 +159,10 @@ void mainboard_romstage_entry(unsigned long bist)
outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38);
cbmem_initted = !cbmem_recovery(s3resume);
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume && cbmem_initted) {
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
- } else {
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC);
- }
-#endif
- printk(BIOS_SPEW, "exit main()\n");
+
+ handoff = romstage_handoff_find_or_add();
+ if (handoff != NULL)
+ handoff->s3_resume = s3resume;
+ else
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
}
diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c
index 2f35c81..6c5f9c9 100644
--- a/src/mainboard/lenovo/x201/mainboard.c
+++ b/src/mainboard/lenovo/x201/mainboard.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <delay.h>
#include <string.h>
@@ -90,7 +91,6 @@ static void fill_ssdt(device_t device)
static void mainboard_enable(device_t dev)
{
- device_t dev0;
u16 pmbase;
dev->ops->init = mainboard_init;
@@ -110,8 +110,7 @@ static void mainboard_enable(device_t dev)
0x10);
/* If we're resuming from suspend, blink suspend LED */
- dev0 = dev_find_slot(0, PCI_DEVFN(0, 0));
- if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
+ if (acpi_is_wakeup_s3())
ec_write(0x0c, 0xc7);
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2);
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 7b8d7f9..961925c 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -180,6 +180,7 @@ void mainboard_romstage_entry(unsigned long bist)
u32 reg32;
int s3resume = 0;
const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 };
+ struct romstage_handoff *handoff;
timestamp_init(timestamp_get());
@@ -277,19 +278,14 @@ void mainboard_romstage_entry(unsigned long bist)
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
}
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume) {
+ quick_ram_check();
+
+ handoff = romstage_handoff_find_or_add();
+ if (handoff != NULL)
+ handoff->s3_resume = s3resume;
+ else
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
- } else {
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
- quick_ram_check();
- }
-#endif
#if CONFIG_LPC_TPM
init_tpm(s3resume);
diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
index b1096d2..6661a5f 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -17,13 +17,13 @@
#include <console/console.h>
#include <device/device.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <delay.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
-#include <arch/io.h>
#include <arch/interrupt.h>
#include <ec/lenovo/pmh7/pmh7.h>
#include <ec/acpi/ec.h>
@@ -79,7 +79,7 @@ int get_cst_entries(acpi_cstate_t **entries)
static void mainboard_init(device_t dev)
{
- device_t dev0, idedev, sdhci_dev;
+ device_t idedev, sdhci_dev;
ec_clr_bit(0x03, 2);
@@ -91,8 +91,7 @@ static void mainboard_init(device_t dev)
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3);
/* If we're resuming from suspend, blink suspend LED */
- dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
- if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
+ if (acpi_is_wakeup_s3())
ec_write(0x0c, 0xc7);
idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index 04c9513..af45095 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -26,6 +26,7 @@
#include <cpu/x86/lapic.h>
#include <lib.h>
#include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
@@ -171,6 +172,7 @@ void mainboard_romstage_entry(unsigned long bist)
u32 reg32;
int s3resume = 0;
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
+ struct romstage_handoff *handoff;
timestamp_init(timestamp_get());
@@ -267,17 +269,9 @@ void mainboard_romstage_entry(unsigned long bist)
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
}
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume) {
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
- } else {
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
- quick_ram_check();
- }
-#endif
+ handoff = romstage_handoff_find_or_add();
+ if (handoff != NULL)
+ handoff->s3_resume = s3resume;
+ else
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
}
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index b7ef1bb..a5b9188 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -27,6 +27,7 @@
#include <cbmem.h>
#include <lib.h>
#include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
#include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
@@ -122,6 +123,7 @@ void mainboard_romstage_entry(unsigned long bist)
int s3resume = 0;
int cbmem_initted;
u16 reg16;
+ struct romstage_handoff *handoff;
/* basic northbridge setup, including MMCONF BAR */
gm45_early_init();
@@ -187,18 +189,10 @@ void mainboard_romstage_entry(unsigned long bist)
init_iommu();
cbmem_initted = !cbmem_recovery(s3resume);
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume && cbmem_initted) {
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
- } else {
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC);
- }
-#endif
- printk(BIOS_SPEW, "exit main()\n");
+
+ handoff = romstage_handoff_find_or_add();
+ if (handoff != NULL)
+ handoff->s3_resume = s3resume;
+ else
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
}
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index aaa6749..af62f12 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -216,28 +216,11 @@ static struct device_operations cpu_bus_ops = {
.scan_bus = 0,
};
-
static void enable_dev(device_t dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
-#if CONFIG_HAVE_ACPI_RESUME
- switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) {
- case SKPAD_NORMAL_BOOT_MAGIC:
- printk(BIOS_DEBUG, "Normal boot.\n");
- acpi_slp_type = 0;
- break;
- case SKPAD_ACPI_S3_MAGIC:
- printk(BIOS_DEBUG, "S3 Resume.\n");
- acpi_slp_type = 3;
- break;
- default:
- printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
- acpi_slp_type = 0;
- break;
- }
-#endif
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 9523333..0ef2a4e 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -21,6 +21,7 @@
#include <device/pci_def.h>
#include <cbmem.h>
#include <halt.h>
+#include <romstage_handoff.h>
#include <string.h>
#include "i945.h"
#include <pc80/mc146818rtc.h>
@@ -197,7 +198,6 @@ static void i945_setup_bars(void)
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC);
printk(BIOS_DEBUG, " done.\n");
/* Wait for MCH BAR to come up */
@@ -898,18 +898,20 @@ void i945_early_initialization(void)
static void i945_prepare_resume(int s3resume)
{
int cbmem_was_initted;
+ struct romstage_handoff *handoff;
cbmem_was_initted = !cbmem_recovery(s3resume);
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume && cbmem_was_initted) {
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
- SKPAD_ACPI_S3_MAGIC);
+ if (s3resume && !acpi_s3_resume_allowed()) {
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+ s3resume = 0;
}
+
+ handoff = romstage_handoff_find_or_add();
+ if (handoff != NULL)
+ handoff->s3_resume = s3resume;
+ else
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
}
void i945_late_initialization(int s3resume)
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 5d18591..848bbaa 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -213,26 +213,6 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
-#if CONFIG_HAVE_ACPI_RESUME
-static void northbridge_init(struct device *dev)
-{
- switch (pci_read_config32(dev, SKPAD)) {
- case SKPAD_NORMAL_BOOT_MAGIC:
- printk(BIOS_DEBUG, "Normal boot.\n");
- acpi_slp_type = 0;
- break;
- case SKPAD_ACPI_S3_MAGIC:
- printk(BIOS_DEBUG, "S3 Resume.\n");
- acpi_slp_type = 3;
- break;
- default:
- printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
- acpi_slp_type = 0;
- break;
- }
-}
-#endif
-
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
};
@@ -242,9 +222,6 @@ static struct device_operations mc_ops = {
.set_resources = mc_set_resources,
.enable_resources = pci_dev_enable_resources,
.acpi_fill_ssdt_generator = generate_cpu_entries,
-#if CONFIG_HAVE_ACPI_RESUME
- .init = northbridge_init,
-#endif
.scan_bus = 0,
.ops_pci = &intel_pci_ops,
};
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 381bfbd..ce399cc 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -222,10 +222,6 @@ enum {
#define D0F0_TOLUD 0xb0
#define D0F0_SKPD 0xdc /* Scratchpad Data */
-#define SKPAD_ACPI_S3_MAGIC 0xcafed00d
-#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe
-
-
#define D0F0_CAPID0 0xe0
#define TSEG 0xac /* TSEG base */
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 06c0a96..3a24b71 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -287,26 +287,6 @@ static void northbridge_init(struct device *dev)
MCHBAR32(0x5500) = 0x00100001;
}
-static void northbridge_enable(device_t dev)
-{
-#if CONFIG_HAVE_ACPI_RESUME
- switch (pci_read_config32(dev, SKPAD)) {
- case 0xcafebabe:
- printk(BIOS_DEBUG, "Normal boot.\n");
- acpi_slp_type = 0;
- break;
- case 0xcafed00d:
- printk(BIOS_DEBUG, "S3 Resume.\n");
- acpi_slp_type = 3;
- break;
- default:
- printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
- acpi_slp_type = 0;
- break;
- }
-#endif
-}
-
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
};
@@ -316,7 +296,6 @@ static struct device_operations mc_ops = {
.set_resources = mc_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
- .enable = northbridge_enable,
.acpi_fill_ssdt_generator = generate_cpu_entries,
.scan_bus = 0,
.ops_pci = &intel_pci_ops,
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 86d1c00..ef97a1a 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -23,6 +23,7 @@
#include <elog.h>
#include <cbmem.h>
#include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
#include "sandybridge.h"
static void sandybridge_setup_bars(void)
@@ -226,19 +227,13 @@ void sandybridge_early_initialization(int chipset_type)
void northbridge_romstage_finalize(int s3resume)
{
- MCHBAR16(SSKPD) = 0xCAFE;
-
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
+ struct romstage_handoff *handoff;
- if (s3resume) {
+ MCHBAR16(SSKPD) = 0xCAFE;
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
- } else {
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
- }
-#endif
+ handoff = romstage_handoff_find_or_add();
+ if (handoff != NULL)
+ handoff->s3_resume = s3resume;
+ else
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
}
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index a67b84d..fe1a07c 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -470,26 +470,6 @@ static void northbridge_init(struct device *dev)
MCHBAR32(0x5500) = 0x00100001;
}
-static void northbridge_enable(device_t dev)
-{
-#if CONFIG_HAVE_ACPI_RESUME
- switch (pci_read_config32(dev, SKPAD)) {
- case 0xcafebabe:
- printk(BIOS_DEBUG, "Normal boot.\n");
- acpi_slp_type=0;
- break;
- case 0xcafed00d:
- printk(BIOS_DEBUG, "S3 Resume.\n");
- acpi_slp_type=3;
- break;
- default:
- printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
- acpi_slp_type=0;
- break;
- }
-#endif
-}
-
static u32 northbridge_get_base_reg(device_t dev, int reg)
{
u32 value;
@@ -521,7 +501,6 @@ static struct device_operations mc_ops = {
.set_resources = mc_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
- .enable = northbridge_enable,
.scan_bus = 0,
.ops_pci = &intel_pci_ops,
.acpi_fill_ssdt_generator = generate_cpu_entries,
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 7e8b988..d1441e8 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -375,7 +375,5 @@ int southbridge_detect_s3_resume(void);
#define SS_CNT 0x50
#define C3_RES 0x54
-#define SKPAD_ACPI_S3_MAGIC 0xcafed00d
-#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe
#endif /* __ACPI__ */
#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */
diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c
index 01fbbfb..b61e068 100644
--- a/src/southbridge/intel/i82801gx/smi.c
+++ b/src/southbridge/intel/i82801gx/smi.c
@@ -19,6 +19,7 @@
#include <device/pci.h>
#include <console/console.h>
#include <arch/io.h>
+#include <arch/acpi.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
@@ -315,16 +316,6 @@ static void smm_relocate(void)
static int smm_handler_copied = 0;
-static int is_wakeup(void)
-{
- device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
-
- if (!dev0)
- return 0;
-
- return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC;
-}
-
static void smm_install(void)
{
/* The first CPU running this gets to copy the SMM handler. But not all
@@ -338,7 +329,7 @@ static void smm_install(void)
/* if we're resuming from S3, the SMM code is already in place,
* so don't copy it again to keep the current SMM state */
- if (!is_wakeup()) {
+ if (!acpi_is_wakeup_s3()) {
/* enable the SMM memory window */
pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
D_OPEN | G_SMRAME | C_BASE_SEG);
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index afe4aa7..af4efcd 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -218,10 +218,6 @@
#define FD_SAD1 (1 << 2) /* SATA #1 */
-#define SKPAD_ACPI_S3_MAGIC 0xcafed00d
-#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe
-
-
#ifndef __ACPI__
#ifndef __ASSEMBLER__
diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c
index dd0915a..34fbad4 100644
--- a/src/southbridge/intel/i82801ix/smi.c
+++ b/src/southbridge/intel/i82801ix/smi.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <console/console.h>
#include <arch/io.h>
+#include <arch/acpi.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
@@ -314,16 +315,6 @@ static void smm_relocate(void)
static int smm_handler_copied = 0;
-static int is_wakeup(void)
-{
- device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
-
- if (!dev0)
- return 0;
-
- return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC;
-}
-
static void smm_install(void)
{
/* The first CPU running this gets to copy the SMM handler. But not all
@@ -337,7 +328,7 @@ static void smm_install(void)
/* if we're resuming from S3, the SMM code is already in place,
* so don't copy it again to keep the current SMM state */
- if (!is_wakeup()) {
+ if (!acpi_is_wakeup_s3()) {
/* enable the SMM memory window */
pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
D_OPEN | G_SMRAME | C_BASE_SEG);
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