[coreboot-gerrit] Patch set updated for coreboot: intel post-car: Separate files for setup_stack_and_mtrrs()
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Thu Nov 10 14:25:26 CET 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15762
-gerrit
commit 8c43c1c42557451674c05b9debbec95104a14677
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Mon Jun 27 13:24:11 2016 +0300
intel post-car: Separate files for setup_stack_and_mtrrs()
Have a common romstage.c file to prepare CAR stack guards.
MTRR setup around cbmem_top() is somewhat northbridge specific,
place stubs under northbridge for platrform that will move
to RELOCATABLE_RAMSTAGE.
Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/car/romstage.c | 51 +++++++++++++++++++++++++++-
src/include/cpu/intel/romstage.h | 23 +++++++++++++
src/northbridge/intel/gm45/ram_calc.c | 6 ++++
src/northbridge/intel/i945/ram_calc.c | 6 ++++
src/northbridge/intel/nehalem/ram_calc.c | 6 ++++
src/northbridge/intel/sandybridge/ram_calc.c | 6 ++++
src/northbridge/intel/x4x/ram_calc.c | 6 ++++
7 files changed, 103 insertions(+), 1 deletion(-)
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index c6df446..d04b6e1 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -1,7 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <console/console.h>
#include <cpu/intel/romstage.h>
+#include <program_loading.h>
+
+#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x800
void * asmlinkage romstage_main(unsigned long bist)
{
+ int i;
+ void *romstage_stack_after_car;
+ const int num_guards = 4;
+ const u32 stack_guard = 0xdeadbeef;
+ u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
+ CONFIG_DCACHE_RAM_SIZE -
+ DCACHE_RAM_ROMSTAGE_STACK_SIZE);
+
+ for (i = 0; i < num_guards; i++)
+ stack_base[i] = stack_guard;
+
mainboard_romstage_entry(bist);
- return (void*)CONFIG_RAMTOP;
+
+ /* Check the stack. */
+ for (i = 0; i < num_guards; i++) {
+ if (stack_base[i] == stack_guard)
+ continue;
+ printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
+ }
+
+ /* Get the stack to use after cache-as-ram is torn down. */
+ if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT))
+ romstage_stack_after_car = (void*)CONFIG_RAMTOP;
+ else
+ romstage_stack_after_car = setup_stack_and_mtrrs();
+
+ return romstage_stack_after_car;
+}
+
+void asmlinkage romstage_after_car(void)
+{
+ /* Load the ramstage. */
+ run_ramstage();
}
diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h
index d443564..1f967ce 100644
--- a/src/include/cpu/intel/romstage.h
+++ b/src/include/cpu/intel/romstage.h
@@ -4,6 +4,29 @@
#include <arch/cpu.h>
void mainboard_romstage_entry(unsigned long bist);
+
+/* romstage_main is called from the cache-as-ram assembly file. The return
+ * value is the stack value to be used for romstage once cache-as-ram is
+ * torn down. The following values are pushed onto the stack to setup the
+ * MTRRs:
+ * +0: Number of MTRRs
+ * +4: MTRR base 0 31:0
+ * +8: MTRR base 0 63:32
+ * +12: MTRR mask 0 31:0
+ * +16: MTRR mask 0 63:32
+ * +20: MTRR base 1 31:0
+ * +24: MTRR base 1 63:32
+ * +28: MTRR mask 1 31:0
+ * +32: MTRR mask 1 63:32
+ * ...
+ */
+void *setup_stack_and_mtrrs(void);
+
+/* romstage_main is called from the cache-as-ram assembly file to prepare
+ * CAR stack guards.*/
void * asmlinkage romstage_main(unsigned long bist);
+/* romstage_after_car() is the C function called after cache-as-ram has
+ * been torn down. It is responsible for loading the ramstage. */
+void asmlinkage romstage_after_car(void);
#endif /* _CPU_INTEL_ROMSTAGE_H */
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 9a65e19..92f1a7f 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -21,6 +21,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <console/console.h>
+#include <cpu/intel/romstage.h>
#include <cbmem.h>
#include "gm45.h"
@@ -105,3 +106,8 @@ void *cbmem_top(void)
{
return (void *) smm_region_start();
}
+
+void *setup_stack_and_mtrrs(void)
+{
+ return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 4349d19..39ede5f 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -20,6 +20,7 @@
#include <cbmem.h>
#include "i945.h"
#include <console/console.h>
+#include <cpu/intel/romstage.h>
static uintptr_t smm_region_start(void)
{
@@ -69,3 +70,8 @@ u32 decode_igd_memory_size(const u32 gms)
return ggc2uma[gms] << 10;
}
+
+void *setup_stack_and_mtrrs(void)
+{
+ return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index 60ac2a7..4d73ee9 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -17,6 +17,7 @@
#include <arch/io.h>
#include <cbmem.h>
+#include <cpu/intel/romstage.h>
#include "nehalem.h"
static uintptr_t smm_region_start(void)
@@ -30,3 +31,8 @@ void *cbmem_top(void)
{
return (void *) smm_region_start();
}
+
+void *setup_stack_and_mtrrs(void)
+{
+ return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c
index fff420a..125f808 100644
--- a/src/northbridge/intel/sandybridge/ram_calc.c
+++ b/src/northbridge/intel/sandybridge/ram_calc.c
@@ -17,6 +17,7 @@
#include <arch/io.h>
#include <cbmem.h>
+#include <cpu/intel/romstage.h>
#include "sandybridge.h"
static uintptr_t smm_region_start(void)
@@ -30,3 +31,8 @@ void *cbmem_top(void)
{
return (void *) smm_region_start();
}
+
+void *setup_stack_and_mtrrs(void)
+{
+ return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 5a6a767..09eec47 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -23,6 +23,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <console/console.h>
+#include <cpu/intel/romstage.h>
#include <northbridge/intel/x4x/x4x.h>
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
@@ -93,3 +94,8 @@ void *cbmem_top(void)
u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG);
return (void*)(ramtop);
}
+
+void *setup_stack_and_mtrrs(void)
+{
+ return (void*)CONFIG_RAMTOP;
+}
More information about the coreboot-gerrit
mailing list