[coreboot-gerrit] New patch to review for coreboot: soc/intel/skylake: move i2c voltage config to own variable
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Thu Nov 10 00:18:37 CET 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17347
-gerrit
commit 09e9370960157768287f1dc56d8fd237ce2ebc62
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Nov 9 17:04:15 2016 -0600
soc/intel/skylake: move i2c voltage config to own variable
In preparation of merging the lpss i2c config structures on
apollolake and skylake move the i2c voltage variable to its
own field. It makes refactoring things easier, and then there's
no reason for a separate SoC specific i2c config structure.
BUG=chrome-os-partner:58889
Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/chell/devicetree.cb | 2 +-
src/mainboard/google/eve/devicetree.cb | 10 +++++-----
src/mainboard/google/glados/devicetree.cb | 2 +-
src/mainboard/google/lars/devicetree.cb | 2 +-
src/mainboard/intel/kunimitsu/devicetree.cb | 2 +-
src/soc/intel/skylake/chip.c | 2 +-
src/soc/intel/skylake/chip.h | 4 ++--
src/soc/intel/skylake/chip_fsp20.c | 2 +-
8 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 230a9a6..238a5a5 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -163,7 +163,7 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # SD
- register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index d825acf..37a5ff0 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -160,11 +160,11 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
- register "i2c[0].voltage" = "I2C_VOLTAGE_3V3" # Touchscreen
- register "i2c[1].voltage" = "I2C_VOLTAGE_3V3" # TPM
- register "i2c[2].voltage" = "I2C_VOLTAGE_1V8" # Touchpad
- register "i2c[3].voltage" = "I2C_VOLTAGE_1V8" # Display
- register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # Audio
+ register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen
+ register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM
+ register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Touchpad
+ register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Display
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Audio
# Enable I2C1 bus early for TPM access
register "i2c[1].early_init" = "1"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 9b74212..d17ef6c 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -163,7 +163,7 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port 1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port 2
- register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 25bd19d..dab95de 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -160,7 +160,7 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
- register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 8dded98..3cdaa06 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -164,7 +164,7 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
- register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 879c157..2703224 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -163,7 +163,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->SkipMpInit = config->FspSkipMpInit;
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
- params->SerialIoI2cVoltage[i] = config->i2c[i].voltage;
+ params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
/*
* To disable Heci, the Psf needs to be left unlocked
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 5a4e85b..81b358b 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -40,8 +40,6 @@ enum skylake_i2c_voltage {
};
struct skylake_i2c_config {
- /* Bus voltage level, default is 3.3V */
- enum skylake_i2c_voltage voltage;
/* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
enum i2c_speed speed;
/* Bus should be enabled prior to ramstage with temporary base */
@@ -201,6 +199,8 @@ struct soc_intel_skylake_config {
u8 SerialIoDevMode[PchSerialIoIndexMax];
/* I2C */
+ /* Bus voltage level, default is 3.3V */
+ enum skylake_i2c_voltage i2c_voltage[SKYLAKE_I2C_DEV_MAX];
struct skylake_i2c_config i2c[SKYLAKE_I2C_DEV_MAX];
/* Camera */
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 98960f9..49569d9 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -203,7 +203,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit;
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
- params->SerialIoI2cVoltage[i] = config->i2c[i].voltage;
+ params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
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