[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: fix memory access beyond array bounds

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d8bb69a451276baf14f17fceeb89790638310990
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Tue Nov 8 21:01:09 2016 +0530

    soc/intel/skylake: fix memory access beyond array bounds
    
    chip.h has a config array PcieRpClkReqNumber which corresponds
    to a FSP UPD parameter, the size is currently set to 20.
    However the size of PcieRpClkReqNumber UPD in FSP2.0 is 24,
    so memcpy (config buffer to UPD buffer) in chip_fsp20.c will read
    beyond the bounds of config array.
    Hence set the size of PcieRpClkReqNumber array based on the FSP in use.
    
    Found-by: Coverity Scan #1365385, #1365386
    
    Change-Id: I937f68ef33f218cd7f9ba5cf3baaec162bca3fc8
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Reviewed-on: https://review.coreboot.org/17292
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/17292 for details.

-gerrit