[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/reef: Tune digitizer I2C frequency to 400kHz
Furquan Shaikh (furquan@google.com)
gerrit at coreboot.org
Wed Nov 9 23:04:44 CET 2016
Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17342
-gerrit
commit 83bcb421b33e7f4183ef1c2453d7ecfd55b4c9e3
Author: Furquan Shaikh <furquan at chromium.org>
Date: Wed Nov 9 10:35:23 2016 -0800
mainboard/google/reef: Tune digitizer I2C frequency to 400kHz
This brings the I2C frequency down to 400kHz wwhich is spec for fast
I2C.
BUG=chrome-os-partner:56246
BRANCH=None
TEST=Verified frequency in kernel.
Change-Id: Ib83c57eec8644903cb9c4b2ab50c94038eb690c1
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
src/mainboard/google/reef/variants/baseboard/devicetree.cb | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 5aa1d32..6c8cd8f 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -95,6 +95,17 @@ chip soc/intel/apollolake
}
}"
+ # Limit digitizer speed to 400kHz with manually tuned values.
+ register "i2c[5]" = "{
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 0xd0,
+ .scl_hcnt = 0x68,
+ .sda_hold = 0x27,
+ }
+ }"
+
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
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