[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/pyro: Set PL1 override to 12000mW

[Kevin Chiu (Kevin.Chiu@quantatw.com)]

Kevin Chiu (Kevin.Chiu at quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17335

-gerrit

commit a2b09cbda1886a933342a576951a81c22f7bfb1b
Author: Kevin Chiu <Kevin.Chiu at quantatw.com>
Date:   Wed Nov 9 14:07:30 2016 +0800

    mainboard/google/pyro: Set PL1 override to 12000mW
    
    Pyro is using APL SoC SKU's with 6W TDP max. As Reef,
    the energy calculation is wrong with the current VR solution.
    Experiments show that SoC TDP max (6W) can be reached
    when RAPL PL1 is set to 12W.
    Therefore, we've inserted 12W override after reading the fused value (6W)
    so that the system can reach the right performance level.
    
    BUG=chrome-os-partner:58112
    BRANCH=master
    TEST=emerge-pyro coreboot chromeos-bootimage
    Change-Id: I6de22d7b2d107f3d26ecfadd4e0904e68318e656
    Signed-off-by: Kevin Chiu <Kevin.Chiu at quantatw.com>
---
 src/mainboard/google/reef/variants/pyro/devicetree.cb | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index a0ba584..61626f9 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -49,6 +49,11 @@ chip soc/intel/apollolake
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
+	# PL1 override 12000 mW: the energy calculation is wrong with the
+	# current VR solution. Experiments show that SoC TDP max (6W) can
+	# be reached when RAPL PL1 is set to 12W.
+	register "tdp_pl1_override_mw" = "12000"
+
 	# Enable Audio Clock and Power gating
 	register "hdaudio_clk_gate_enable" = "1"
 	register "hdaudio_pwr_gate_enable" = "1"