[coreboot-gerrit] Patch set updated for coreboot: soc/intel: Add MSR to support enabling turbo frequency
Martin Roth (martinroth@google.com)
gerrit at coreboot.org
Wed Nov 9 00:33:05 CET 2016
Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17211
-gerrit
commit ddb3f8720ae559e72be91ce4fb6d7e7894ca0830
Author: Shaunak Saha <shaunak.saha at intel.com>
Date: Wed Nov 2 10:52:23 2016 -0700
soc/intel: Add MSR to support enabling turbo frequency
This patch adds definition FREQ_LIMIT_RATIO MSR.
FREQ_LIMIT_RATIO register allows to determine the ratio limits
to be used to limit frequency.
BUG=chrome-os-partner:58158
BRANCH=None
Change-Id: I50a792accbaab1bff313fd00574814d7dbba1f6b
Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
src/include/cpu/intel/speedstep.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 09906df..40234d5 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -46,7 +46,7 @@
#define MSR_PMG_IO_BASE_ADDR 0xe3
#define MSR_PMG_IO_CAPTURE_ADDR 0xe4
#define MSR_EXTENDED_CONFIG 0xee
-
+#define FREQ_LIMIT_RATIO 0x1AD
typedef struct {
uint8_t dynfsb : 1; /* whether this is SLFM */
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