[coreboot-gerrit] Patch set updated for coreboot: soc/intel: Add MSR to support enabling turbo frequency

[Shaunak Saha (shaunak.saha@intel.com)]

Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17211

-gerrit

commit bbd7978e6ad6718ccb1ff91e4c597bd8018d3398
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Wed Nov 2 10:52:23 2016 -0700

    soc/intel: Add MSR to support enabling turbo frequency
    
    This patch adds definition for IA32_PERF_CTL and
    FREQ_LIMIT_RATIO MSR's. FREQ_LIMIT_RATIO register allows
    to determine the ratio limits to be used to limit frequency.
    PERF_CTL is Performance Control MSR. BIOS makes request
    for a new Performance state (P-state) by writing to this MSR.
    
    BUG=chrome-os-partner:58158
    BRANCH=None
    
    Change-Id: I50a792accbaab1bff313fd00574814d7dbba1f6b
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
 src/include/cpu/intel/speedstep.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 09906df..40234d5 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -46,7 +46,7 @@
 #define MSR_PMG_IO_BASE_ADDR	0xe3
 #define MSR_PMG_IO_CAPTURE_ADDR	0xe4
 #define MSR_EXTENDED_CONFIG	0xee
-
+#define FREQ_LIMIT_RATIO	0x1AD
 
 typedef struct {
 	uint8_t dynfsb : 1; /* whether this is SLFM */