[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add save/restore variable MRC cache

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17237

-gerrit

commit 1d7f5405191973186b9587c24f9b383dc1a3388c
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Fri Nov 4 16:18:30 2016 -0700

    soc/intel/apollolake: Add save/restore variable MRC cache
    
    Apollolake MRC cache is divided into two regions: constant and variable.
    Currently they are clubbed together. Since variable data changes across
    cold reboot it triggers invalidation of the whole cache region. This
    change declubs the data, adds routines to load/store variable data on
    flash.
    
    BUG=chrome-os-partner:57515
    TEST=with patch series applied: cold reboot, make sure MRC is not
    updated. Do S3 suspend/resume cycle.
    
    Change-Id: I374519777abe9b9a1e6cceae5318decd405bb527
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/Kconfig    |  4 ++++
 src/soc/intel/apollolake/romstage.c | 37 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 187214a..f4bc7ab 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -162,6 +162,10 @@ config CACHE_MRC_SETTINGS
 	bool
 	default y
 
+config MRC_SETTINGS_VARIABLE_DATA
+	bool
+	default y
+
 config FSP_M_ADDR
 	hex
 	default 0xfef40000
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 1f6a38f..c8f30b6 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -41,8 +41,17 @@
 #include <string.h>
 #include <timestamp.h>
 
+#include <lib.h>
+#include "soc/intel/common/mrc_cache.h"
+
 static struct chipset_power_state power_state CAR_GLOBAL;
 
+static const uint8_t hob_variable_guid[16] = {
+	0x7d, 0x14, 0x34, 0xa0, 0x0c, 0x69, 0x54, 0x41,
+	0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42,
+};
+
+
 /* High Performance Event Timer Configuration */
 #define P2SB_HPTC				0x60
 #define P2SB_HPTC_ADDRESS_ENABLE		(1 << 7)
@@ -107,7 +116,8 @@ asmlinkage void car_stage_entry(void)
 	bool s3wake;
 	struct chipset_power_state *ps = car_get_var_ptr(&power_state);
 	void *smm_base;
-	size_t smm_size;
+	size_t smm_size, var_size;
+	const void *new_var_data;
 	uintptr_t tseg_base;
 
 	timestamp_add_now(TS_START_ROMSTAGE);
@@ -119,6 +129,13 @@ asmlinkage void car_stage_entry(void)
 
 	s3wake = fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);
+
+	/* Stash variable MRC data and let cache system update it later */
+	new_var_data = fsp_find_extension_hob_by_guid(hob_variable_guid,
+							&var_size);
+	if (new_var_data)
+		mrc_cache_stash_vardata(new_var_data, var_size);
+
 	if (postcar_frame_init(&pcf, 1*KiB))
 		die("Unable to initialize postcar frame.\n");
 
@@ -170,6 +187,8 @@ static void fill_console_params(FSPM_UPD *mupd)
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)
 {
+	const struct mrc_saved_data *msd;
+
 	fill_console_params(mupd);
 	mainboard_memory_init_params(mupd);
 
@@ -193,6 +212,22 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)
 	 * skip HECI2 reset.
 	 */
 	mupd->FspmConfig.EnableS3Heci2 = 0;
+
+	/*
+	 * Apollolake splits MRC cache into two parts: constant and variable.
+	 * The constant part is not expected to change often and variable is.
+	 * Currently variable part consists of parameters that change on cold
+	 * boots such as scrambler seed and some memory controller registers.
+	 * Scrambler seed is vital for S3 resume case because attempt to use
+	 * wrong/missing key renders DRAM contents useless.
+	 */
+
+	printk(BIOS_DEBUG, "MRC variable data ");
+	if (mrc_cache_get_vardata(&msd) >= 0) {
+		mupd->FspmConfig.VariableNvsBufferPtr = (void*) msd->data;
+		printk(BIOS_DEBUG, "loaded\n");
+	} else
+		printk(BIOS_DEBUG, " missing/invalid\n");
 }
 
 __attribute__ ((weak))