[coreboot-gerrit] New patch to review for coreboot: mainboard/tyan/s8226: transition away from device_t

[Antonello Dettori (dev@dettori.io)]

Antonello Dettori (dev at dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17309

-gerrit

commit 0634a3e76d97ec63a4084a194edb75b154ad064a
Author: Antonello Dettori <dev at dettori.io>
Date:   Tue Nov 8 18:44:46 2016 +0100

    mainboard/tyan/s8226: transition away from device_t
    
    Replace the use of the old device_t definition inside
    mainboard/tyan/s8226.
    
    Change-Id: I41729fc03518a7804ae224c773967453a7ab60a7
    Signed-off-by: Antonello Dettori <dev at dettori.io>
---
 src/mainboard/tyan/s8226/BiosCallOuts.c | 4 ++--
 src/mainboard/tyan/s8226/romstage.c     | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c
index 0fa9742..fea32cb 100644
--- a/src/mainboard/tyan/s8226/BiosCallOuts.c
+++ b/src/mainboard/tyan/s8226/BiosCallOuts.c
@@ -35,7 +35,7 @@
 
 static UINT8 select_socket(UINT8 socket_id)
 {
-	device_t sm_dev       = PCI_DEV(0, 0x14, 0); //SMBUS
+	pci_devfn_t sm_dev       = PCI_DEV(0, 0x14, 0); //SMBUS
 	UINT8    value        = 0;
 	UINT8    gpio52_to_49 = 0;
 
@@ -67,7 +67,7 @@ static UINT8 select_socket(UINT8 socket_id)
 
 static void restore_socket(UINT8 original_value)
 {
-	device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
+	pci_devfn_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
 	pci_write_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL, original_value);
 
 	// TODO: Restore previous GPIO48 configurations?
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index ea877b7..7460f20 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -43,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x31);
 
 	/* For serial port. */
-	device_t dev = PCI_DEV(0, 0x14, 3);
+	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev, 0x44, 0xff03ffd5);
 
 	/* Halt if there was a built in self test failure */