[coreboot-gerrit] New patch to review for coreboot: intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZE
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Tue Nov 8 00:30:59 CET 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17268
-gerrit
commit 1f085fbbed96c0fc48aa59c53b71a06cd3b574ef
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Jul 26 14:03:31 2016 +0300
intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZE
Not referenced in code.
Change-Id: Iea91f4418eb122fb647ec0f4f42cb786e8eadf23
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/soc/intel/baytrail/Kconfig | 13 +++----------
src/soc/intel/braswell/Kconfig | 13 +++----------
src/soc/intel/broadwell/Kconfig | 7 -------
3 files changed, 6 insertions(+), 27 deletions(-)
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 4009785..f4c7e11 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -99,9 +99,9 @@ endif # HAVE_MRC
# | MRC usage |
# | |
# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
-# | Stack |\
-# | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE
-# | v |/
+# | Stack |
+# | | |
+# | v |
# +-------------+
# | ^ |
# | | |
@@ -131,13 +131,6 @@ config DCACHE_RAM_MRC_VAR_SIZE
help
The amount of cache-as-ram region required by the reference code.
-config DCACHE_RAM_ROMSTAGE_STACK_SIZE
- hex
- default 0x800
- help
- The amount of anticipated stack usage from the data cache
- during pre-RAM ROM stage execution.
-
config RESET_ON_INVALID_RAMSTAGE_CACHE
bool "Reset the system on S3 wake when ramstage cache invalid."
default n
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index b587988..ddd7051 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -75,9 +75,9 @@ config SMM_RESERVED_SIZE
# Cache As RAM region layout:
#
# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
-# | Stack |\
-# | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE
-# | v |/
+# | Stack |
+# | | |
+# | v |
# +-------------+
# | ^ |
# | | |
@@ -97,13 +97,6 @@ config DCACHE_RAM_SIZE
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
-config DCACHE_RAM_ROMSTAGE_STACK_SIZE
- hex
- default 0x800
- help
- The amount of anticipated stack usage from the data cache
- during pre-ram ROM stage execution.
-
config RESET_ON_INVALID_RAMSTAGE_CACHE
bool "Reset the system on S3 wake when ramstage cache invalid."
default n
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 517fd21..29b5bfe 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -106,13 +106,6 @@ config DCACHE_RAM_MRC_VAR_SIZE
help
The amount of cache-as-ram region required by the reference code.
-config DCACHE_RAM_ROMSTAGE_STACK_SIZE
- hex
- default 0x2000
- help
- The amount of anticipated stack usage from the data cache
- during pre-ram ROM stage execution.
-
config HAVE_MRC
bool "Add a Memory Reference Code binary"
help
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