[coreboot-gerrit] Patch set updated for coreboot: mainboard/intel/kblrvp: Add Chrome EC switch

[Naresh Solanki (naresh.solanki@intel.com)]

Naresh Solanki (naresh.solanki at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17248

-gerrit

commit a7c14bf9666d916a49f379138e40b753940fa734
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date:   Sun Nov 6 14:05:35 2016 +0530

    mainboard/intel/kblrvp: Add Chrome EC switch
    
    Add Chrome EC switch to enable building with/without Chrome EC.
    
    Change-Id: Iaa8102cba0a454a24149d29f044a2284cd29e28b
    Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
 src/mainboard/intel/kblrvp/acpi/ec.asl        |  3 +-
 src/mainboard/intel/kblrvp/acpi/mainboard.asl |  2 ++
 src/mainboard/intel/kblrvp/chromeos.c         | 41 +++++++++++++++++----------
 3 files changed, 30 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl
index 2203e2f..7d7ff2f 100644
--- a/src/mainboard/intel/kblrvp/acpi/ec.asl
+++ b/src/mainboard/intel/kblrvp/acpi/ec.asl
@@ -22,6 +22,7 @@
 
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
-
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 /* ACPI code for EC functions */
 #include <ec/google/chromeec/acpi/ec.asl>
+#endif
diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
index 1b8fe43..5d2b307 100644
--- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl
+++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
@@ -16,6 +16,7 @@
 
 #include "../gpio.h"
 
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 Scope (\_SB)
 {
 	Device (LID0)
@@ -34,6 +35,7 @@ Scope (\_SB)
 		Name (_HID, EisaId ("PNP0C0C"))
 	}
 }
+#endif
 
 /*
  * LPC Trusted Platform Module
diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c
index a9704da..fc1bcd2 100644
--- a/src/mainboard/intel/kblrvp/chromeos.c
+++ b/src/mainboard/intel/kblrvp/chromeos.c
@@ -40,8 +40,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
 		{-1, ACTIVE_HIGH, 0, "power"},
 		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
-		{GPIO_EC_IN_RW, ACTIVE_HIGH,
-			gpio_get(GPIO_EC_IN_RW), "EC in RW"},
 	};
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
@@ -49,8 +47,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_lid_switch(void)
 {
-	/* Read lid switch state from the EC. */
-	return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
+	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+		/* Read lid switch state from the EC. */
+		return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
+
+	/* Lid always open */
+	return 1;
 }
 
 int get_developer_mode_switch(void)
@@ -61,31 +63,40 @@ int get_developer_mode_switch(void)
 
 int get_recovery_mode_switch(void)
 {
-	/* Check for dedicated recovery switch first. */
-	if (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY)
+	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+		/* Check for dedicated recovery switch first. */
+		if (google_chromeec_get_switches() &
+			EC_SWITCH_DEDICATED_RECOVERY)
 		return 1;
 
-	/* Otherwise check if the EC has posted the keyboard recovery event. */
-	return !!(google_chromeec_get_events_b() &
-		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+		/* Otherwise check if the EC has posted the keyboard recovery
+		 * event. */
+		return !!(google_chromeec_get_events_b() &
+			  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+	}
+
+	return 0;
 }
 
 int clear_recovery_mode_switch(void)
 {
-	/* Clear keyboard recovery event. */
-	return google_chromeec_clear_events_b(
-		EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+		/* Clear keyboard recovery event. */
+		return google_chromeec_clear_events_b(
+			EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+
+	return 0;
 }
 
 int get_write_protect_state(void)
 {
-	/* Read PCH_WP GPIO. */
-	return gpio_get(GPIO_PCH_WP);
+	/* No write protect */
+	return 0;
 }
 
 static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
-	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 };
 
 void mainboard_chromeos_acpi_generate(void)