[coreboot-gerrit] New patch to review for coreboot: nb/intel/i945: Clean up native VGA graphic init

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17253

-gerrit

commit 2b76ce07e483c48b1dd42e901b7dd8a9b34555e7
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Sun Nov 6 18:34:34 2016 +0100

    nb/intel/i945: Clean up native VGA graphic init
    
    This code was simply copied from the Pineview northbridge
    and many writes to registers are not necessary.
    
    TESTED on Thinkpad X60 with VGA display connected.
    
    Change-Id: I68cf6c71670ed1050416c57369b0bf1a18b9f65c
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/northbridge/intel/i945/gma.c | 20 --------------------
 1 file changed, 20 deletions(-)

diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index bb0bb73..7e57d0f 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -417,11 +417,6 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
 	write32(pmmio + VGA0, 0x200074);
 	write32(pmmio + VGA1, 0x200074);
 
-	write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN);
-	write32(pmmio + DSPCLK_GATE_D, 0);
-	write32(pmmio + FW_BLC, 0x03060106);
-	write32(pmmio + FW_BLC2, 0x00000306);
-
 	write32(pmmio + ADPA, ADPA_DAC_ENABLE
 			| ADPA_PIPE_A_SELECT
 			| ADPA_USE_VGA_HVPOLARITY
@@ -430,13 +425,6 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
 			| ADPA_DPMS_ON
 			);
 
-	write32(pmmio + 0x7041c, 0x0);
-
-	write32(pmmio + DPLL_MD(0), 0x3);
-	write32(pmmio + DPLL_MD(1), 0x3);
-	write32(pmmio + DSPCNTR(1), 0x1000000);
-	write32(pmmio + PIPESRC(1), 0x027f01df);
-
 	vga_misc_write(0x67);
 	const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
 		    0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
@@ -503,12 +491,6 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
 
 	mdelay(1);
 
-	write32(pmmio + FDI_RX_CTL(0), 0x00002040);
-	mdelay(1);
-	write32(pmmio + FDI_RX_CTL(0), 0x80002050);
-	write32(pmmio + FDI_TX_CTL(0), 0x00044000);
-	mdelay(1);
-	write32(pmmio + FDI_TX_CTL(0), 0x80044000);
 	write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
 
 	write32(pmmio + VGACNTRL, 0x0);
@@ -525,8 +507,6 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
 
 	write32(pmmio + DSPFW3, 0x7f3f00c1);
 	write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH);
-	write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5));
-	write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9));
 
 	/* Set up GTT.  */