[coreboot-gerrit] New patch to review for coreboot: soc/intel/common: Enable SPI and NVM drivers in pre-ram stages
Furquan Shaikh (furquan@google.com)
gerrit at coreboot.org
Sun Nov 6 08:24:38 CET 2016
Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17239
-gerrit
commit 995a35dc43434bba3b2fc54e2fe988f8f4c7ac6f
Author: Furquan Shaikh <furquan at chromium.org>
Date: Sat Nov 5 23:46:10 2016 -0700
soc/intel/common: Enable SPI and NVM drivers in pre-ram stages
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified that spi region can be protected in romstage using nvm
functions.
Change-Id: Iba32b0828b7f2078ee3dbaeb0c6abd2157307fb2
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
src/soc/intel/common/Makefile.inc | 2 ++
src/soc/intel/common/nvm.c | 14 +++++++++++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 38903a0..4abe524 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -10,7 +10,9 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
+romstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_SPI_PROTECT) += spi.c
romstage-y += util.c
romstage-$(CONFIG_MMA) += mma.c
diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c
index 6b86faf..b0ca814 100644
--- a/src/soc/intel/common/nvm.c
+++ b/src/soc/intel/common/nvm.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <arch/early_variables.h>
#include <stdint.h>
#include <stddef.h>
#include <bootmode.h>
@@ -28,10 +29,12 @@
* address space for reading. Also this module assumes an area it erased
* when all bytes read as all 0xff's. */
-static struct spi_flash *flash;
+static struct spi_flash *gflash CAR_GLOBAL;
static int nvm_init(void)
{
+ struct spi_flash *flash = car_get_var(gflash);
+
if (flash != NULL)
return 0;
@@ -41,6 +44,7 @@ static int nvm_init(void)
printk(BIOS_DEBUG, "Could not find SPI device\n");
return -1;
}
+ car_set_var(gflash, flash);
return 0;
}
@@ -81,6 +85,9 @@ int nvm_erase(void *start, size_t size)
{
if (nvm_init() < 0)
return -1;
+
+ struct spi_flash *flash = car_get_var(gflash);
+
return flash->erase(flash, nvm_mmio_to_flash_offset(start), size);
}
@@ -89,6 +96,9 @@ int nvm_write(void *start, const void *data, size_t size)
{
if (nvm_init() < 0)
return -1;
+
+ struct spi_flash *flash = car_get_var(gflash);
+
return flash->write(flash, nvm_mmio_to_flash_offset(start), size, data);
}
@@ -98,6 +108,8 @@ int nvm_is_write_protected(void)
if (nvm_init() < 0)
return -1;
+ struct spi_flash *flash = car_get_var(gflash);
+
if (IS_ENABLED(CONFIG_CHROMEOS)) {
u8 sr1;
u8 wp_gpio;
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