[coreboot-gerrit] Patch set updated for coreboot: soc/intel/common: Enable SPI NVM functions in pre-RAM stages

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17234

-gerrit

commit 8849609b16fcd07bb229dd5554748e0e217b912c
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Fri Nov 4 15:37:27 2016 -0700

    soc/intel/common: Enable SPI NVM functions in pre-RAM stages
    
    Put global variable into CAR global.
    
    BUG=chrome-os-partner:57515
    TEST=with patch series applied: cold reboot, make sure MRC is not
    updated. Do S3 suspend/resume cycle.
    
    Change-Id: I35ea29096abcdde482b99d90db022b7c7bc95c29
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/common/Makefile.inc |  1 +
 src/soc/intel/common/nvm.c        | 16 +++++++++++++++-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 38903a0..51b6f86 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -13,6 +13,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
 romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 romstage-y += util.c
 romstage-$(CONFIG_MMA) += mma.c
+romstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
 
 postcar-y += util.c
 postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c
index 6b86faf..5af73d5 100644
--- a/src/soc/intel/common/nvm.c
+++ b/src/soc/intel/common/nvm.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/early_variables.h>
 #include <stdint.h>
 #include <stddef.h>
 #include <bootmode.h>
@@ -28,10 +29,12 @@
  * address space for reading. Also this module assumes an area it erased
  * when all bytes read as all 0xff's. */
 
-static struct spi_flash *flash;
+static struct spi_flash *gflash CAR_GLOBAL;
 
 static int nvm_init(void)
 {
+	struct spi_flash *flash = car_get_var(gflash);
+
 	if (flash != NULL)
 		return 0;
 
@@ -41,6 +44,7 @@ static int nvm_init(void)
 		printk(BIOS_DEBUG, "Could not find SPI device\n");
 		return -1;
 	}
+	car_set_var(gflash, flash);
 
 	return 0;
 }
@@ -79,25 +83,35 @@ int nvm_is_erased(const void *start, size_t size)
 
 int nvm_erase(void *start, size_t size)
 {
+	struct spi_flash *flash;
+
 	if (nvm_init() < 0)
 		return -1;
+	flash =  car_get_var(gflash);
 	return flash->erase(flash, nvm_mmio_to_flash_offset(start), size);
 }
 
 /* Write data to NVM. Returns 0 on success < 0 on error.  */
 int nvm_write(void *start, const void *data, size_t size)
 {
+	struct spi_flash *flash;
+
 	if (nvm_init() < 0)
 		return -1;
+	flash = car_get_var(gflash);
 	return flash->write(flash, nvm_mmio_to_flash_offset(start), size, data);
 }
 
 /* Read flash status register to determine if write protect is active */
 int nvm_is_write_protected(void)
 {
+	struct spi_flash *flash;
+
 	if (nvm_init() < 0)
 		return -1;
 
+	flash = car_get_var(gflash);
+
 	if (IS_ENABLED(CONFIG_CHROMEOS)) {
 		u8 sr1;
 		u8 wp_gpio;