[coreboot-gerrit] New patch to review for coreboot: vendorcode/intel/fsp2_0: Add new fields to FSPM UPD on Apollolake
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Sat Nov 5 00:58:35 CET 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17236
-gerrit
commit 4702ef246d6875729abe48c8ee82f696fc71798f
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Fri Nov 4 16:21:58 2016 -0700
vendorcode/intel/fsp2_0: Add new fields to FSPM UPD on Apollolake
BUG=chrome-os-partner:57515
TEST=with patch series applied: cold reboot, make sure MRC is not
updated. Do S3 suspend/resume cycle.
Change-Id: I533f504d9e713a28788ad32f6ba399a2930b2384
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
.../intel/fsp/fsp2_0/apollolake/FspmUpd.h | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h
index d2d2461..21c1110 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h
@@ -796,33 +796,38 @@ typedef struct {
Enable FSP to trigger reset instead of returning reset request. 0x00: Return the
Return Status from FSP if a reset is required. (default); 0x01: Perform Reset inside
FSP instead of returning from the API.
- 0x0:Disabled, 0x1:Enabled
+ 0x0:Disabled, 0x1:Eabled
**/
UINT8 EnableResetSystem;
/** Offset 0x014C - Enable HECI2 in S3 resume path
Enable HECI2 in S3 resume path. 0x00: Skip HECI2 initialization in S3 resume. ;
0x01: Enable HECI2 in S3 resume path.(Default)
- 0x0:Disabled, 0x1:Enabled
+ 0x0:Disabled, 0x1:Eabled
**/
UINT8 EnableS3Heci2;
-/** Offset 0x014D
+ UINT8 unused[3];
+/** Offset 0x0150
+**/
+ VOID* VariableNvsBufferPtr;
+
+/** Offset 0x0154
**/
- UINT8 ReservedFspmUpd[3];
+ UINT8 ReservedFspmUpd[12];
} FSP_M_CONFIG;
/** Fsp M Test Configuration
**/
typedef struct {
-/** Offset 0x0150
+/** Offset 0x0160
**/
UINT32 Signature;
-/** Offset 0x0154
+/** Offset 0x0164
**/
- UINT8 ReservedFspmTestUpd[28];
+ UINT8 ReservedFspmTestUpd[12];
} FSP_M_TEST_CONFIG;
/** Fsp M Restricted Configuration
@@ -854,7 +859,7 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x0150
+/** Offset 0x0160
**/
FSP_M_TEST_CONFIG FspmTestConfig;
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