[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: Implement SPI flash status register read

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d36ed272b2d2d082889a7f21414904badc2c2936
Author: Furquan Shaikh <furquan at chromium.org>
Date:   Tue Nov 1 21:33:12 2016 -0700

    soc/intel/apollolake: Implement SPI flash status register read
    
    This was a dummy implementation until now which returned -1 always. Add
    support for reading SPI flash status register (srp0).
    
    BUG=chrome-os-partner:59267
    BRANCH=None
    TEST=Verified by enabling and disabling write-protect on reef that the
    value of SRP0 changes accordingly in status register read.
    
    Change-Id: Ib1349605dd87c4a087e416f52a8256b1eaac4f4c
    Signed-off-by: Furquan Shaikh <furquan at chromium.org>
    Reviewed-on: https://review.coreboot.org/17205
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/17205 for details.

-gerrit